SDAA429A June   2026  – October 2026 MSPM0G5187

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 MSPM0G5187 with TinyEngine NPU
  6. 3 Edge AI Toolchains
    1. 3.1 TI Edge AI Studio
    2. 3.2 TI Tiny ML Tensorlab
    3. 3.3 TI Neural Network Compiler
  7. 4 Rapid Prototyping Through TI Edge AI Studio
    1. 4.1 Project Setup
    2. 4.2 Data Capture
      1. 4.2.1 Hardware Setup
      2. 4.2.2 Feature Overview
    3. 4.3 Data Import
      1. 4.3.1 Classification Task
      2. 4.3.2 Regression Task
      3. 4.3.3 Forecasting Task
      4. 4.3.4 Annotation List
    4. 4.4 Data Annotation
    5. 4.5 Model Training
      1. 4.5.1 Training Parameter
      2. 4.5.2 Toolchain Dependency
    6. 4.6 Performance Reports
    7. 4.7 Model Export
  8. 5 Advanced Development Through TI Tiny ML Tensorlab
    1. 5.1 Environment Setup
    2. 5.2 Data Acquisition
      1. 5.2.1 Data Retrieval
      2. 5.2.2 Data Validation
    3. 5.3 Model Architecture Iterative Refactoring
      1. 5.3.1 Baseline Implementation
      2. 5.3.2 Refactoring With PyTorch Built-in Modules
      3. 5.3.3 Data Pipeline Optimization
      4. 5.3.4 Transition to CNN Architecture
    4. 5.4 Model Export
    5. 5.5 Quantization-Aware Training
    6. 5.6 Model Compilation
  9. 6 Edge AI Application: Digit Recognition
    1. 6.1 LeNet-5 Variant CNN Model
    2. 6.2 NPU/CPU Performance Comparison
  10. 7 Edge AI Application: Waveform Classifier
    1. 7.1 Feature Extraction
    2. 7.2 Time-Series Classification Model
    3. 7.3 Model Memory Considerations
    4. 7.4 NPU/CPU Performance Comparison
  11. 8 Summary
  12. 9 References
  13. 10Revision History

7.3 Model Memory Considerations

Developing edge AI designs on resource-constrained embedded platforms requires balancing a rigid, three-way optimization triad: algorithmic performance (accuracy, latency), non-volatile storage (FLASH/ROM), and run-time memory (SRAM).

  • Algorithmic Performance: encompasses both inference accuracy and latency, which are primarily shaped by the model architecture - including network depth, layer width, and operator complexity.
  • Static Storage Memory (Flash/ROM): This is primarily determined by the model's total parameter count (weights and biases). In a fully quantized INT8 pipeline, each parameter maps directly to exactly one byte of Flash storage. Consequently, deeper networks with expanded channel widths linearly increases the static binary size. Sometimes, the variations in the input feature dimensions can also influence this static memory usage (for example, in fully-connected layer).
  • Dynamic Runtime Memory (SRAM/RAM): This is governed by the input feature size and the resulting activation tensors (feature maps) across intermediate layers. As a time-series slice propagates through the network, the processing core must allocate temporary workspaces to store layer inputs and outputs. Longer input temporal windows or higher feature dimensions exponentially inflate this peak runtime RAM requirement.

Driven by these hardware realities, deploying at the edge forces a departure from traditional accuracy-first mentalities. Instead, navigating a successful deployment demands a meticulous trade-off, balancing raw model performance directly against the hard physical boundaries of static Flash and peak dynamic SRAM.

To illustrate this relationship, Table 7-5 quantifies the memory footprint and resource utilization of waveform classifier across varying model sizes and input feature configurations (test with Edge AI Studio 1.6.1 Cloud Version).

Table 7-5 Model Memory Analysis
Model Variant (Parameter)Flash (ROM) SizeRAM Size at Input = 64RAM Size at Input = 128RAM Size at Input = 256
TimeSeries_Generic_1KApproximately 5.6KBApproximately 2.7KBApproximately 5.3KBApproximately 10.4KB
TimeSeries_Generic_4KApproximately 9.9KBApproximately 1.2KBApproximately 1.7KBApproximately 2.7KB
TimeSeries_Generic_13KApproximately 21.4KBApproximately 2.3KBApproximately 3.3KBApproximately 5.3KB

Across all input dimensions, the smallest model (TimeSeries_Generic_1K) consistently consumes two to four times more runtime RAM than the larger models (TimeSeries_Generic_4K and TimeSeries_Generic_13K). This counterintuitive behavior stems from the fact that parameter count and runtime memory are driven by fundamentally different architectural decisions. The 1K model relies on a shallow topology that lacks early downsampling, causing large, high-resolution feature maps to persist in memory throughout the intermediate layers. In contrast, 4K and 13K models adopt deeper architectures with strided convolutions at the front-end of the network, which immediately reduce the temporal dimensions and significantly decrease the size of intermediate runtime tensors.