SDAA429A June   2026  – October 2026 MSPM0G5187

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 MSPM0G5187 with TinyEngine NPU
  6. 3 Edge AI Toolchains
    1. 3.1 TI Edge AI Studio
    2. 3.2 TI Tiny ML Tensorlab
    3. 3.3 TI Neural Network Compiler
  7. 4 Rapid Prototyping Through TI Edge AI Studio
    1. 4.1 Project Setup
    2. 4.2 Data Capture
      1. 4.2.1 Hardware Setup
      2. 4.2.2 Feature Overview
    3. 4.3 Data Import
      1. 4.3.1 Classification Task
      2. 4.3.2 Regression Task
      3. 4.3.3 Forecasting Task
      4. 4.3.4 Annotation List
    4. 4.4 Data Annotation
    5. 4.5 Model Training
      1. 4.5.1 Training Parameter
      2. 4.5.2 Toolchain Dependency
    6. 4.6 Performance Reports
    7. 4.7 Model Export
  8. 5 Advanced Development Through TI Tiny ML Tensorlab
    1. 5.1 Environment Setup
    2. 5.2 Data Acquisition
      1. 5.2.1 Data Retrieval
      2. 5.2.2 Data Validation
    3. 5.3 Model Architecture Iterative Refactoring
      1. 5.3.1 Baseline Implementation
      2. 5.3.2 Refactoring With PyTorch Built-in Modules
      3. 5.3.3 Data Pipeline Optimization
      4. 5.3.4 Transition to CNN Architecture
    4. 5.4 Model Export
    5. 5.5 Quantization-Aware Training
    6. 5.6 Model Compilation
  9. 6 Edge AI Application: Digit Recognition
    1. 6.1 LeNet-5 Variant CNN Model
    2. 6.2 NPU/CPU Performance Comparison
  10. 7 Edge AI Application: Waveform Classifier
    1. 7.1 Feature Extraction
    2. 7.2 Time-Series Classification Model
    3. 7.3 Model Memory Considerations
    4. 7.4 NPU/CPU Performance Comparison
  11. 8 Summary
  12. 9 References
  13. 10Revision History

2 MSPM0G5187 with TinyEngine NPU

MSPM0G5187 microcontrollers (MCUs) are part of the MSP highly integrated, ultra-low-power 32-bit MCU family based on the enhanced Arm® Cortex®-M0+ 32-bit core platform, operating at up to 80MHz frequency. These MCUs offer a blend of cost optimization and design flexibility for applications requiring up to 128KB of flash memory in small packages or high pin count packages (up to 64 pins). These devices include a USB2.0-FS interface, digital audio interface, TinyEngine NPU, and provide excellent low power performance across the operating temperature range.

The hardware NPU is a highly optimized core for deep convolutional neural networks (CNNs), supporting machine learning inference using pre-trained models. This works in conjunction with the on-chip CPU to provide higher performance and lower power consumption for CNN inference. With capability for 640–2560MOPS (Mega Operations Per Second), the NPU enables 90x lower latency than software implementations and consumes less than 2μA in standby mode.

Figure 2-1 shows the top-level view of the modules within the chip.

MSP CPU/NPU System StructureFigure 2-1 MSP CPU/NPU System Structure

MSPM0 with NPU system shares the on-chip memory including non-volatile FLASH memory and volatile RAM memory. The system RAM supports read/write with CPU or NPU. Additionally, NPU has a dedicated RAM for CNN inference. The Edge AI model must fit within the available FLASH memory range, and the peak RAM requirements must fit within the available system RAM.