SDAA429A June   2026  – October 2026 MSPM0G5187

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 MSPM0G5187 with TinyEngine NPU
  6. 3 Edge AI Toolchains
    1. 3.1 TI Edge AI Studio
    2. 3.2 TI Tiny ML Tensorlab
    3. 3.3 TI Neural Network Compiler
  7. 4 Rapid Prototyping Through TI Edge AI Studio
    1. 4.1 Project Setup
    2. 4.2 Data Capture
      1. 4.2.1 Hardware Setup
      2. 4.2.2 Feature Overview
    3. 4.3 Data Import
      1. 4.3.1 Classification Task
      2. 4.3.2 Regression Task
      3. 4.3.3 Forecasting Task
      4. 4.3.4 Annotation List
    4. 4.4 Data Annotation
    5. 4.5 Model Training
      1. 4.5.1 Training Parameter
      2. 4.5.2 Toolchain Dependency
    6. 4.6 Performance Reports
    7. 4.7 Model Export
  8. 5 Advanced Development Through TI Tiny ML Tensorlab
    1. 5.1 Environment Setup
    2. 5.2 Data Acquisition
      1. 5.2.1 Data Retrieval
      2. 5.2.2 Data Validation
    3. 5.3 Model Architecture Iterative Refactoring
      1. 5.3.1 Baseline Implementation
      2. 5.3.2 Refactoring With PyTorch Built-in Modules
      3. 5.3.3 Data Pipeline Optimization
      4. 5.3.4 Transition to CNN Architecture
    4. 5.4 Model Export
    5. 5.5 Quantization-Aware Training
    6. 5.6 Model Compilation
  9. 6 Edge AI Application: Digit Recognition
    1. 6.1 LeNet-5 Variant CNN Model
    2. 6.2 NPU/CPU Performance Comparison
  10. 7 Edge AI Application: Waveform Classifier
    1. 7.1 Feature Extraction
    2. 7.2 Time-Series Classification Model
    3. 7.3 Model Memory Considerations
    4. 7.4 NPU/CPU Performance Comparison
  11. 8 Summary
  12. 9 References
  13. 10Revision History

6.2 NPU/CPU Performance Comparison

The Edge AI model can be deployed to hardware via TI Neural Network Compiler, targeting either the dedicated hardware NPU or the host CPU. The TinyEngine NPU is a dedicated hardware accelerator specifically designed to execute neural network computations with high efficiency, delivering significantly reduced inference latency and energy compared to a general-purpose CPU.

To facilitate performance evaluation, the MSPM0 SDK provides both NPU and CPU implementation examples for user benchmarking, refers to:

Table 7-9 summarizes the performance comparison between the NPU-based and CPU-based Edge AI designs for the digit recognition application.

Table 6-3 NPU/CPU Performance Comparison
Performance MetricNPU-Based DesignCPU-Based Design
AccuracyApproximately 99%Approximately 99%
Flash Usage73KB68KB
RAM Usage10.9KB8.1KB
Inference Latency6.05ms89.81ms
Inference Energy (AVG)170.38uJ2,447.45uJ

The NPU-based design achieves approximately 15 times lower inference latency compared to the CPU-based implementation and effectively reduces the energy consumption per inference by approximately 96%, making it a highly efficient choice for power-sensitive edge applications.