SDAA435 July   2026 TAA5212 , TAA5242 , TAC5211 , TAC5242 , TAD5212 , TAD5212-Q1 , TAD5242

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Detailed Description
    1. 2.1 Internal Noise (Within the IC)
      1. 2.1.1 Noise Shaping and Filtering Out the Noise
      2. 2.1.2 Avoiding Noise Coupling between Internal Digital and Analog Modules
    2. 2.2 External Noise
      1. 2.2.1 Clock Jitter
      2. 2.2.2 Power Supplies
    3. 2.3 Noise from PCB Design and Routing
  6. 3Summary
  7. 4References

2.2.1 Clock Jitter

The clock jitter will introduce sampling error which results in degradation of SNR. Jitter can result in distortion and increased noise floor. The increased noise floor has direct effect on the degradation of SNR. Equation 4 quantifies the effect of jitter error on SNR as

Equation 4. SNR=20log⁡(Vp/22πfin Vp.tj/2)=-20log⁡(2πfintj)

Where tj, fin and Vp are the jitter, input frequency and amplitude of the signal respectively. You can read more about the details of jitter and SNR relationship and the derivation of the above equation in the provided Ref.4.