SDAA515 August   2026 TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Detailed Description
    1. 2.1  DDR Inline ECC Overview
      1. 2.1.1 Benefits of DDR Inline ECC
    2. 2.2  ECC Protection Region Planning
    3. 2.3  ECC Capacity Considerations
    4. 2.4  ECC Configuration Guidelines
      1. 2.4.1 ECC Generation Phase
      2. 2.4.2 ECC Protection Phase
    5. 2.5  Why DDR Priming Is Required
    6. 2.6  DDR Priming Using DRU
    7. 2.7  DRU Resource Allocation
    8. 2.8  SBL Integration
    9. 2.9  Recommended Initialization Flow
    10. 2.10 Performance Evaluation
    11. 2.11 Troubleshooting Common DDR Inline ECC Deployment Issues
      1. 2.11.1 ECC Checking Enabled Before Priming
      2. 2.11.2 Incorrect ECC Region Configuration
      3. 2.11.3 Read-Modify-Write Disabled
    12. 2.12 Validation and Debug Considerations
  6. 3Summary
  7. 4References

2.1 DDR Inline ECC Overview

TDA4VE DDR Inline ECC Architecture Figure 2-1 TDA4VE DDR Inline ECC Architecture

This architecture provides continuous protection against memory corruption while minimizing software overhead.

DDR Inline ECC operates transparently as part of the DDR subsystem.

During memory write operations:

  1. User data is written to DDR.
  2. The ECC engine calculates ECC parity information.
  3. ECC information is stored automatically alongside protected data.

During memory read operations:

  1. Data and ECC information are retrieved.
  2. The ECC engine performs syndrome checking.
  3. Single-bit errors are corrected automatically.
  4. Double-bit errors are detected and reported.

The mechanism provides continuous runtime protection without requiring software involvement during normal operation.