SDAA515 August   2026 TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Detailed Description
    1. 2.1  DDR Inline ECC Overview
      1. 2.1.1 Benefits of DDR Inline ECC
    2. 2.2  ECC Protection Region Planning
    3. 2.3  ECC Capacity Considerations
    4. 2.4  ECC Configuration Guidelines
      1. 2.4.1 ECC Generation Phase
      2. 2.4.2 ECC Protection Phase
    5. 2.5  Why DDR Priming Is Required
    6. 2.6  DDR Priming Using DRU
    7. 2.7  DRU Resource Allocation
    8. 2.8  SBL Integration
    9. 2.9  Recommended Initialization Flow
    10. 2.10 Performance Evaluation
    11. 2.11 Troubleshooting Common DDR Inline ECC Deployment Issues
      1. 2.11.1 ECC Checking Enabled Before Priming
      2. 2.11.2 Incorrect ECC Region Configuration
      3. 2.11.3 Read-Modify-Write Disabled
    12. 2.12 Validation and Debug Considerations
  6. 3Summary
  7. 4References

2.10 Performance Evaluation

The reference implementation was evaluated using a 4GB DDR configuration.

DDR Capacity Priming Time
4GB Approximately 147ms

The result demonstrates that DRU-based initialization can efficiently generate ECC information across the entire protected DDR address space while maintaining acceptable start-up overhead.

Actual priming time can vary depending on:

  • DDR frequency
  • DRU configuration
  • Protected memory size
  • System initialization sequence
ECC Error Reporting Flow Figure 2-4 ECC Error Reporting Flow

Figure 2-4 illustrates the ECC error reporting path.

Correctable errors (CE) are automatically corrected by the DDR subsystem, while uncorrectable errors (UE) are reported through the ESM for software handling.