SLAA870 February   2019 AFE7422 , AFE7444

 

  1.   Evaluating the frequency hopping capability of the AFE74xx
    1.     Trademarks
    2. 1 Introduction
    3. 2 Phase Coherency vs Phase Continuity
    4. 3 AFE74xx Architecture
      1. 3.1 AFE74xx Receivers: Multiband DDC
      2. 3.2 AFE74xx Transmitters: Multiband DUC
      3. 3.3 Numerically Controlled Oscillator (NCO)
        1. 3.3.1 Programming the NCO frequency
          1. 3.3.1.1 Example: Programming NCO to 1700MHz
        2. 3.3.2 Direct Digital Synthesis (DDS) Mode
    5. 4 Frequency Hopping Methods
      1. 4.1 Maintaining Phase Continuity
        1. 4.1.1 Phase Continuous Hop Time
          1. 4.1.1.1 Serial Peripheral Interface (SPI)
          2. 4.1.1.2 Test Setup
          3. 4.1.1.3 Software Configuration
          4. 4.1.1.4 Test Results
      2. 4.2 Maintaining Phase Coherency
        1. 4.2.1 TX NCO Hopping Using SPI
          1. 4.2.1.1 TX NCO Switch Using SPI Hop Time
            1. 4.2.1.1.1 Software Configuration
            2. 4.2.1.1.2 Test Results
          2. 4.2.1.2 AFE74xx DAC Settling Time
            1. 4.2.1.2.1 Hardware Setup
            2. 4.2.1.2.2 Software Configuration
            3. 4.2.1.2.3 Test Results
        2. 4.2.2 RX NCO Hopping Using the GPIO Pins
          1. 4.2.2.1 Test Setup
          2. 4.2.2.2 Software Configuration
          3. 4.2.2.3 Test Results
    6. 5 NCO Frequency Resolution Versus Hop Time
    7. 6 Fast Frequency Hopping With the Load and Switch
    8. 7 Register Addresses
    9. 8 References

4.1.1.1 Serial Peripheral Interface (SPI)

Understanding the SPI instruction cycle is critical to approximating the time required for the AFE74xx to hop frequencies after the command is received through SPI. Each SPI read/write operation is framed by signal SDEN (serial data enable bar) asserted low. The first two bytes are the instruction cycle that identifies the following data transfer cycle as read or write, as well as the 15-bit address to be accessed. The last byte labeled D7 through D0 in the SPI instruction cycle contains the data written to the designated AFE74xx register address.

spi_stream_write_ex_slase83.gifFigure 11. SPI Bus Write Cycle

The reprogramming the NCO frequency in the AFE74xx DAC, the first four SPI writes program the 32-bit NCO accumulator word. The last two SPI writes toggle the NCO reset bit to reflect the change in frequency on the designated DAC output.