SLAA890A December 2019 – August 2021 MSP430FR2000 , MSP430FR2032 , MSP430FR2033 , MSP430FR2100 , MSP430FR2110 , MSP430FR2111 , MSP430FR2153 , MSP430FR2155 , MSP430FR2310 , MSP430FR2311 , MSP430FR2353 , MSP430FR2355 , MSP430FR2422 , MSP430FR2433 , MSP430FR2475 , MSP430FR2476 , MSP430FR2512 , MSP430FR2522 , MSP430FR2532 , MSP430FR2533 , MSP430FR2632 , MSP430FR2633 , MSP430FR2672 , MSP430FR2673 , MSP430FR2675 , MSP430FR2676 , MSP430FR4131 , MSP430FR4132 , MSP430FR4133
Table 2-1 lists the key timing and linearity parameters to compare a few products with the FR2xx/FR4xx ADC and the ADC12_B. For more details, see the device-specific data sheet.
| Parameter | Description | Condition | Device | ||
|---|---|---|---|---|---|
| MSP430FR2355 | MSP430FR2311 | MSP430FR58xx | |||
| FR2xx/FR4xx ADC 12-Bit Mode | FR2xx/FR4xx ADC 10-Bit Configuration | ADC12_B Single-Ended Mode | |||
| fADCCLK | ADC clock frequency | 4.4 MHz max | 5.5 MHz max | 5.4 MHz max | |
| tSample | Sampling time | Notes | 0.61 µs min(1) | 2 µs min | 1 µs min |
| tCONVERT | Conversion time | 14 × 1/fADCCLK | 12 × 1/fADCCLK(3) | 14 × 1/fADC12CLK(2) | |
| EI | Integral linearity error | Veref+ reference | ±2.5 LSB | ±2 LSB | ±2.2 LSB |
| ED | Differential linearity error | Veref+ reference | ±1 LSB | ±1 LSB | -0.99 + 1 LSB |
| EO | Offset error | Veref+ reference | ±1.5 LSB | ±6.5 mV | ±1.5 mV |
| EG | Gain error | Veref+ reference | ±3 LSB | ±2 LSB | ±2.5 LSB |
| ET | Total unadjusted error | Veref+ reference | ±4 LSB | ±2 LSB | ±3.5 LSB |