SLAAE33 September   2021 DAC43204 , DAC43401 , DAC43701 , DAC43701-Q1 , DAC53204 , DAC53401 , DAC53701 , DAC53701-Q1 , LM555 , LMC555 , NA555 , NE555 , SA555 , SE555 , TLC555

 

  1.   Trademarks
  2. 1Introduction
  3. 2Functional Overview of 555 Timers vs. Smart DACs
  4. 3Pulse Generator with Variable Frequency and Variable Duty Cycle
  5. 4Analog Input to PWM Output
  6. 5General Purpose Input (GPI) to PWM Output
  7. 6Comparator with Hysteresis
  8. 7Trade-offs and Conclusions

5 General Purpose Input (GPI) to PWM Output

Using a principle of operation similar to the analog input to PWM output circuit, it is possible for the system designer to create fixed PWM outputs based on a combination of GPIs. The CONT input to the 555 timer has an internal resistor divider with a nominal pull-up value of 100 kΩ and a pull-down value of 200 kΩ. Figure 5-1 shows a circuit where GPI1 and GPI2 can be driven to states of 0 V or VDD to adjust the voltage at the CONT pin based on the collective impedance of the internal voltage divider circuit.

Figure 5-1 555 Timer Configured for General Purpose Input to PWM

The TINA-TI simulation results shown in Figure 5-2 use R1 = 100 kΩ and R2 = 50 kΩ to create four fixed CONT input voltage levels of 4.39 V, 3.33 V, 2.42 V, and 1.6 V based on the four states of GPI1 and GPI2. A decoupling capacitor is connected to the CONT pin to reduce glitches on the pin during transitions. The circuit then converts these fixed voltages at the CONT pin to PWM outputs using the same principle of operation as the analog input to PWM output circuit.

VS = 5 V, RA = 12 kΩ, C = 2 nF, TRIG = 100-kHz square wave with 98% duty cycle, R1 = 100 kΩ, R2 = 50 kΩ
Figure 5-2 TINA-TI Simulation Results for GPI to PWM Output Using a 555 Timer

GPIs can also be added to a smart DAC to create multiple fixed duty cycle PWM outputs. Adding two resistors to the DAC53701 feedback network shown in Figure 5-3 creates two new GPI pins. The voltage at the feedback pin changes depending on the level of GPI1 and GPI2. The four resistors in the feedback network can be modified to get custom threshold levels at the DAC53701 feedback pin. The voltage at the feedback pin, along with the margin-high and margin-low voltages of the triangular or sawtooth waveform being generated by the CWG, determine the duty cycle of the PWM output. The slew rate, code step, margin-high and margin-low codes determine the frequency.

Figure 5-3 DAC53701 Configured for General Purpose Input to PWM

Figure 5-4 shows the simulation results with R1-4 creating 4 voltage steps at 4 V, 3 V, 2 V, and 1 V that produce corresponding PWM duty cycles of 20%, 40%, 60%, and 80% respectively on the DAC53701 output.

VS = 5 V, MARGIN_HIGH_CODE = 1023, MARGIN_LOW_CODE = 0, CODE_STEP = 16, SLEW_RATE = 4 µs/step, MARGIN_HIGH = 5 V, MARGIN_LOW = 0 V, VDAC = 2-kHz triangle wave, R1 = 5 kΩ, R2 = 2.5 kΩ, R3 = 5 kΩ, R4 = 5 kΩ
Figure 5-4 TINA-TI Simulation Results for GPI to PWM Output Using a DAC53701

In both the analog input to PWM and GPI to PWM applications, the voltage to duty-cycle function is non-linear in 555 timers and creates duty-cycle error on the order of 5%. The DAC53701 smart DAC voltage presents a superior solution by having linear duty-cycle function with a less than 1% duty-cycle error.