SLAAE71 December   2022 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G1518 , MSPM0G1519 , MSPM0G3105 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3518 , MSPM0G3518-Q1 , MSPM0G3519 , MSPM0G3519-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Overview
  4. 2Low-Power Features in PMCU
    1. 2.1 Overview
      1. 2.1.1 Power Domains and Power Modes
      2. 2.1.2 Power Management (PMU)
        1. 2.1.2.1 Supply Supervisors
        2. 2.1.2.2 Peripheral Power Control
        3. 2.1.2.3 VBOOST for Analog Muxes
      3. 2.1.3 Clock Module (CKM)
        1. 2.1.3.1 Oscillators
        2. 2.1.3.2 Clocks
      4. 2.1.4 System Controller (SYSCTL)
        1. 2.1.4.1 Asynchronous Fast Clock Requests
        2. 2.1.4.2 Shutdown Mode Handling
  5. 3Low-Power Optimization
    1. 3.1 Low-Power Basics
    2. 3.2 MSPM0 Low-Power Feature Use
      1. 3.2.1 Low-Power Modes
      2. 3.2.2 System Clock and Peripheral Operation Frequency
      3. 3.2.3 I/O Configuration
      4. 3.2.4 Event Manager
      5. 3.2.5 Analog Peripheral Low-Power Features
      6. 3.2.6 Run Code From RAM
    3. 3.3 Software Coding Strategies
    4. 3.4 Hardware Design Strategies
  6. 4Power Consumption Measurement and Evaluation
    1. 4.1 Current Evaluation
    2. 4.2 Current Measurement
      1. 4.2.1 Current Measurement

2.1.4.1 Asynchronous Fast Clock Requests

Peripherals can be configured to asynchronously assert a hardware request to the SYSCTL for a fast clock source (32 MHz) from SYSOSC, even if the device is operating in STOP or STANDBY mode. This mechanism is ideal for applications where the MCLK/ULPCLK tree is normally sourced from either LFCLK (at 32 kHz) or SYSOSC (at 4 MHz), but a faster clock is temporarily needed to quickly handle a peripheral event peripheral activity. The peripheral support information can get from Table 2-4.

Table 2-4 Peripheral Support for Asynchronous Fast Clock Requests
Peripheral Purpose Request Source
RTC Fast CPU wake from RTC event RTC IRQ to CPU
TIMG0 and TIMG1 Fast CPU wake from TIMG0/TIMG1 event TIMG0 or TIMG1 IRQ to CPU
GPIO Fast CPU wake from GPIO event GPIO activity
Comparator Fast wake from a comparator event Comparator event
SPI Temporarily use fast clock for bit clock generation SPI activity
I2C Temporarily use fast clock for bit clock generation I2C activity
UART Temporarily use a fast clock for baud rate generation UART activity
ADC Temporarily run the SYSOSC to support timer-triggered ADC operation from a low-power mode ADC

The SYSCTL can be configured to generate an asynchronous fast clock request upon any IRQ request to the CPU with 32-MHz clock rate. This provides the lowest latency interrupt handling when the system is running at the LFCLK rate (32 kHz).