SLAAEB9A February   2024  – August 2025 MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G1518 , MSPM0G1519 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3518 , MSPM0G3518-Q1 , MSPM0G3519 , MSPM0G3519-Q1

 

  1.   1
  2. 1Description
  3. 2Required Peripherals
  4. 3Design Steps
  5. 4Design Considerations
  6. 5Software Flow Chart
  7. 6Application Code
  8. 7Additional Resources
  9. 8Revision History
  10.   Trademarks
  11. 9E2E

Design Steps

  1. Determine the minimum required ADC sampling frequency. This must be at least twice the bandwidth of the input signal.
  2. Determine the desired rejection coefficient. The rejection coefficients in a single pole IIR filter governs the rate of decay of the filter over frequency. The rejection coefficient is sometimes referred to as the beta (β) value, or the decay value.
    1. There are different tools for IIR filter coefficient calculation, which is not discussed in this document.
  3. Convert the filter coefficient to a fixed point value.
    1. In the example code, a Q8 (eight fractional bits) representation is used. Perform this conversion using the IQMath library or by multiplying the coefficients by 2n where n is the desired number of fractional bits. Verify that the selected data type can hold these values without overflowing.
    2. The filter coefficients are constant values and can be contained in flash to save room in SRAM if desired.