SLAAEU5A June 2025 – September 2025 TAS2780 , TAS2781
In this configuration, both PVDDH and PVDDL supply rails are externally provided and used for Class-D switching, and the Y-Bridge feature is enabled.
The TAS278x devices integrate a mechanism to monitor the absolute amplitude of the incoming audio stream to determine the appropriate supply rail—PVDDH or PVDDL. When the audio signal exceeds a programmable Low Voltage Signaling (LVS) threshold (configured as either fixed or relative), the Class-D stage switches to the higher voltage rail (PVDDH) to prevent signal clipping. If the signal remains below this threshold for a period longer than the hysteresis duration—defined by the LVS_HYS[3:0] register bits—the amplifier transitions to the lower voltage rail (PVDDL) to conserve power. When the signal again exceeds the threshold, the supply switches back to PVDDH.
By default, the LVS threshold is set relative to the PVDDL voltage (LVS_DET = 1). The relative threshold level is configured using the LVS_RTH[3:0] register bits, with a default value of 0.7V. Alternatively, setting LVS_DET = 0 enables a fixed LVS threshold defined by the LVS_FTH[4:0] register bits. The LVS threshold is referenced against the output signal level and expressed in dBFS.
The relative threshold voltage at which the amplifier switches from PVDDL to PVDDH is calculated as:
Relative Threshold (Vp) = (PVDDL × Class-D Efficiency – Relative Threshold Headroom) / Inflection Factor
Where:
For example, for PVDDL = 5V, Relative Threshold for Y-Bridge switching = (5 × 0.85 – 0.7) / 1.2 = 2.96 Vp
This intelligent rail-switching mechanism enables the Y-Bridge architecture to maintain audio performance while significantly improving power efficiency, particularly at lower output levels.
| Address | Field [Bits] | Type | Reset | Description |
|---|---|---|---|---|
| 0x37 | LVS_DET[7] | RW | A8h | LVS detection threshold for PWR_MODE1: 0h = Fixed 1h = Relative to PVDDL voltage (default) |
| 0x37 | LVS_FTH[4:0] | RW | A8h | LVS Fixed threshold for PWR_MODE1: CDS_MODE=0h 00h = -18.5dBFS 01h = - 18.25dBFS ….….... 08h = - 16.5dBFS (default) ….….... 1Eh = -11dBFS 1Fh = - 10.75dBFS |
| 0x6A | LVS_RTH[3:0] | RW | 12h | LVS Relative Threshold Headroom for PWR_MODE1: CDS_MODE=0h 0h = 0.5V 1h = 0.6V 2h = 0.7V (default) ….….….…. Eh = 1.9V Fh = 2V |
| 0x36 | LVS_HYST[3:0] | RW | ADh | PVDDH to PVDDL Hysteresis time (PWR_MODE1 and PWR_MODE2) 0h - 9h = Reserved Ah = 1ms Bh = 10ms Ch = 20ms Dh = 50ms (default) Eh = 75ms Fh = 100ms *For sampling rates fs < 48 ksps multiply the above values by 48/fs |
| 0x14-0x17 | CLASSD_EFF[31:0] | RW | 6CCCCCCCh | Class-D Efficiency set to a EFF (%) value dec2hex [round (EFF*2^31)] |