5 PWR_MODE2 [CDS_MODE = 11]

In this configuration, only the PVDDH rail is supplied externally, while the PVDDL voltage is generated internally by the device. Both PVDDH and PVDDL are used for Class-D switching, and the Y-Bridge feature is enabled in this mode.

The amplifier monitors the audio signal level and, when this exceeds a fixed Low Voltage Signaling (LVS) threshold of –71.5 dBFS (default, set through the LVS_TH_LOW[2:1] register bits), the Class-D output switches from PVDDL to PVDDH. In this mode, only idle channel switching occurs on the PVDDL rail, while active audio playback uses PVDDH once the signal crosses the threshold.

To fully utilize the Y-Bridge functionality in PWR_MODE2, this is essential that the PVDDH supply is at least 2.5V higher than the internally generated PVDDL. For example, if PVDDL is internally set to 4.8V, PVDDH needs to be no less than 7.3V. To safeguard this requirement, the under-voltage protection threshold for PVDDH needs to be configured using the PVDDH_UV_TH[5:0] register bits. Setting this threshold appropriately makes sure the voltage headroom is maintained for seamless Y-Bridge operation.

Note, that if PVDDH drops below (PVDDL + 2.5V), the Y-Bridge feature can be disabled and the Class-D output can remain on PVDDH, regardless of signal level.

Additionally, the transition from PVDDL to PVDDH (or vice versa) in response to the audio signal crossing the LVS threshold is not instantaneous. A programmable delay governs this transition and can be configured using the CDS_DLY[1:0] register bits. This delay setting allows fine-tuning of the switching behavior to balance responsiveness and audio performance.