SLASFC2A January   2024  – March 2025 TAC5112-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements: I2C Interface
    7. 5.7  Switching Characteristics: I2C Interface
    8. 5.8  Timing Requirements: SPI
    9. 5.9  Switching Characteristics: SPI
    10. 5.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 5.11 Switching Characteristics: TDM, I2S or LJ Interface
    12. 5.12 Timing Requirements: PDM Digital Microphone Interface
    13. 5.13 Switching Characteristics: PDM Digital Microphone Interface
    14. 5.14 Timing Diagrams
    15. 5.15 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Serial Interfaces
        1. 6.3.1.1 Control Serial Interfaces
        2. 6.3.1.2 Audio Serial Interfaces
          1. 6.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 6.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 6.3.1.2.3 Left-Justified (LJ) Interface
        3. 6.3.1.3 Using Multiple Devices With Shared Buses
      2. 6.3.2  Phase-Locked Loop (PLL) and Clock Generation
      3. 6.3.3  Input Channel Configurations
      4. 6.3.4  Output Channel Configurations
      5. 6.3.5  Reference Voltage
      6. 6.3.6  Programmable Microphone Bias
      7. 6.3.7  Digital PDM Microphone Record Channel
      8. 6.3.8  Incremental ADC (IADC) Mode
      9. 6.3.9  Signal-Chain Processing
        1. 6.3.9.1 ADC Signal-Chain
          1. 6.3.9.1.1  6 to 4 Input Select Multiplexer (6:4 MUX)
          2. 6.3.9.1.2  Programmable Channel Gain and Digital Volume Control
          3. 6.3.9.1.3  Programmable Channel Gain Calibration
          4. 6.3.9.1.4  Programmable Channel Phase Calibration
          5. 6.3.9.1.5  Programmable Digital High-Pass Filter
          6. 6.3.9.1.6  Programmable Digital Biquad Filters
          7. 6.3.9.1.7  Programmable Channel Summer and Digital Mixer
          8. 6.3.9.1.8  Configurable Digital Decimation Filters
            1. 6.3.9.1.8.1 Linear-phase filters
              1. 6.3.9.1.8.1.1 Sampling Rate: 8kHz or 7.35kHz
              2. 6.3.9.1.8.1.2 Sampling Rate: 16kHz or 14.7kHz
              3. 6.3.9.1.8.1.3 Sampling Rate: 24kHz or 22.05kHz
              4. 6.3.9.1.8.1.4 Sampling Rate: 32kHz or 29.4kHz
              5. 6.3.9.1.8.1.5 Sampling Rate: 48kHz or 44.1kHz
              6. 6.3.9.1.8.1.6 Sampling Rate: 96kHz or 88.2kHz
              7. 6.3.9.1.8.1.7 Sampling Rate: 192kHz or 176.4kHz
            2. 6.3.9.1.8.2 Low-latency Filters
              1. 6.3.9.1.8.2.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.9.1.8.2.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.9.1.8.2.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.9.1.8.2.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.9.1.8.2.5 Sampling Rate: 192kHz or 176.4kHz
            3. 6.3.9.1.8.3 Ultra Low-latency Filters
              1. 6.3.9.1.8.3.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.9.1.8.3.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.9.1.8.3.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.9.1.8.3.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.9.1.8.3.5 Sampling Rate: 192kHz or 176.4kHz
          9. 6.3.9.1.9  Automatic Gain Controller (AGC)
          10. 6.3.9.1.10 Voice Activity Detection (VAD)
          11. 6.3.9.1.11 Ultrasonic Activity Detection (UAD)
        2. 6.3.9.2 DAC Signal-Chain
          1. 6.3.9.2.1 Programmable Channel Gain and Digital Volume Control
          2. 6.3.9.2.2 Programmable Channel Gain Calibration
          3. 6.3.9.2.3 Programmable Digital High-Pass Filter
          4. 6.3.9.2.4 Programmable Digital Biquad Filters
          5. 6.3.9.2.5 Programmable Digital Mixer
          6. 6.3.9.2.6 Configurable Digital Interpolation Filters
            1. 6.3.9.2.6.1 Linear-phase filters
              1. 6.3.9.2.6.1.1 Sampling Rate: 8kHz or 7.35kHz
              2. 6.3.9.2.6.1.2 Sampling Rate: 16kHz or 14.7kHz
              3. 6.3.9.2.6.1.3 Sampling Rate: 24kHz or 22.05kHz
              4. 6.3.9.2.6.1.4 Sampling Rate: 32kHz or 29.4kHz
              5. 6.3.9.2.6.1.5 Sampling Rate: 48kHz or 44.1kHz
              6. 6.3.9.2.6.1.6 Sampling Rate: 96kHz or 88.2kHz
              7. 6.3.9.2.6.1.7 Sampling Rate: 192kHz or 176.4kHz
              8. 6.3.9.2.6.1.8 Sampling Rate: 384kHz or 352.8kHz
              9. 6.3.9.2.6.1.9 Sampling Rate 768kHz or 705.6kHz
            2. 6.3.9.2.6.2 Low-latency Filters
              1. 6.3.9.2.6.2.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.9.2.6.2.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.9.2.6.2.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.9.2.6.2.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.9.2.6.2.5 Sampling Rate: 192kHz or 176.4kHz
            3. 6.3.9.2.6.3 Ultra-Low-Latency Filters
              1. 6.3.9.2.6.3.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.9.2.6.3.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.9.2.6.3.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.9.2.6.3.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.9.2.6.3.5 Sampling Rate 192kHz or 176.4kHz
      10. 6.3.10 Interrupts, Status, and Digital I/O Pin Multiplexing
      11. 6.3.11 Power Tune Mode
    4. 6.4 Device Functional Modes
      1. 6.4.1 Sleep Mode or Software Shutdown
      2. 6.4.2 Active Mode
      3. 6.4.3 Software Reset
    5. 6.5 Programming
      1. 6.5.1 Control Serial Interfaces
        1. 6.5.1.1 I2C Control Interface
          1. 6.5.1.1.1 General I2C Operation
          2. 6.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers
            1. 6.5.1.1.2.1 I2C Single-Byte Write
            2. 6.5.1.1.2.2 I2C Multiple-Byte Write
            3. 6.5.1.1.2.3 I2C Single-Byte Read
            4. 6.5.1.1.2.4 I2C Multiple-Byte Read
        2. 6.5.1.2 SPI Control Interface
  8. 7 Register Maps
    1. 7.1 Device Configuration Registers
      1. 7.1.1 Book0_P0 Registers
      2. 7.1.2 B0_P1 Registers
      3. 7.1.3 Book0_Page3 Registers
    2. 7.2 Programmable Coefficient Registers
      1. 7.2.1  Programmable Coefficient Registers: Page 8
      2. 7.2.2  Programmable Coefficient Registers: Page 9
      3. 7.2.3  Programmable Coefficient Registers: Page 10
      4. 7.2.4  Programmable Coefficient Registers: Page 11
      5. 7.2.5  Programmable Coefficient Registers: Page 15
      6. 7.2.6  Programmable Coefficient Registers: Page 16
      7. 7.2.7  Programmable Coefficient Registers: Page 17
      8. 7.2.8  Programmable Coefficient Registers: Page 18
      9. 7.2.9  Programmable Coefficient Registers: Page 19
      10. 7.2.10 Programmable Coefficient Registers: Page 25
      11. 7.2.11 Programmable Coefficient Registers: Page 26
      12. 7.2.12 Programmable Coefficient Registers: Page 27
      13. 7.2.13 Programmable Coefficient Registers: Page 28
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Performance Plots
      5. 8.2.5 Example Device Register Configuration Script for EVM Setup
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 AVDD_MODE for 1.8V Operation
      2. 8.3.2 IOVDD_IO_MODE for 1.8V and 1.2V Operation
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.3.1.3 Using Multiple Devices With Shared Buses

The device has many supported features and flexible options that can be used in the system to seamlessly connect multiple TAC5112-Q1 devices by sharing a single common I2C or SPI control bus and an audio serial interface bus. This architecture enables multiple applications to be applied to a system that require a microphone or speaker array for beam-forming operation, audio conferencing, noise cancellation, and so forth. Figure 6-14 shows a diagram of multiple TAC5112-Q1 devices in a configuration where the control and audio data buses are shared.

TAC5112-Q1 Multiple TAC5112-Q1 Devices With Shared Control and Audio Data Buses Figure 6-14 Multiple TAC5112-Q1 Devices With Shared Control and Audio Data Buses

The TAC5112-Q1 consists of the following features to enable seamless connection and interaction of multiple devices using a shared bus:

  • Supports up to four pin-programmable I2C target addresses
  • I2C broadcast simultaneously writes to (or triggers) all TAC5112-Q1 devices
  • Supports up to 32 configuration input/output channel slots for the audio serial interface
  • Tri-state feature (with enable and disable) for the unused audio data slots of the device
  • Supports a bus-holder feature (with enable and disable) to keep the last driven value on the audio bus
  • The GPIOx, GPI1 or GPO1 pin can be configured as a secondary input/output data lane or as a secondary audio serial interface
  • The GPIOx, GPI1 or GPO1 pin can be used in a daisy-chain configuration of multiple TAC5112-Q1 devices
  • Supports one BCLK cycle data latching timing to relax the timing requirement for the high-speed interface
  • Programmable controller and target options for both primary and secondary audio serial interface
  • Ability to synchronize the multiple devices for the simultaneous sampling requirement across devices
  • Inter Channel Gain Alignment (ICGA) feature to align the DAC Channel gain across devices.
See the Multiple TAC5x1x Devices With a Shared TDM and I2C/SPI Bus application report for further details.