SLASFE0 July   2025 MSPM0H3216-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes (PT, RUK, RGZ, RHB, DGS32, DGS28, RGE, DGS20 Packages)
    3. 6.3 Signal Descriptions
      1.      11
      2.      12
      3.      13
      4.      14
      5.      15
      6.      16
      7.      17
      8.      18
      9.      19
      10.      20
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Thermal Information
    4. 7.4  Supply Current Characteristics
      1. 7.4.1 RUN/SLEEP Modes
      2. 7.4.2 STOP/STANDBY Modes
    5. 7.5  Power Supply Sequencing
      1. 7.5.1 POR and BOR
      2. 7.5.2 Power Supply Ramp
    6. 7.6  Flash Memory Characteristics
    7. 7.7  Timing Characteristics
    8. 7.8  Clock Specifications
      1. 7.8.1 System Oscillator (SYSOSC)
      2. 7.8.2 Low Frequency Oscillator (LFOSC)
      3. 7.8.3 High Frequency Crystal/Clock
      4. 7.8.4 Low Frequency Crystal/Clock
    9. 7.9  Digital IO
      1. 7.9.1  Electrical Characteristics
      2. 7.9.2 Switching Characteristics
    10. 7.10 ADC
      1. 7.10.1 Electrical Characteristics
      2. 7.10.2 Switching Characteristics
      3. 7.10.3 Linearity Parameters
      4. 7.10.4 Typical Connection Diagram
    11. 7.11 Temperature Sensor
    12. 7.12 VREF
      1. 7.12.1 Voltage Characteristics
      2. 7.12.2 Electrical Characteristics
    13. 7.13 I2C
      1. 7.13.1 I2C Characteristics
      2. 7.13.2 I2C Filter
      3. 7.13.3 I2C Timing Diagram
    14. 7.14 SPI
      1. 7.14.1 SPI
      2. 7.14.2 SPI Timing Diagram
    15. 7.15 UART
    16. 7.16 TIMx
    17. 7.17 Windowed Watchdog Characteristics
    18. 7.18 Emulation and Debug
      1. 7.18.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  Overview
    2. 8.2  CPU
    3. 8.3  Operating Modes
      1. 8.3.1 Functionality by Operating Mode (MSPM0H321x)
    4. 8.4  Power Management Unit (PMU)
    5. 8.5  Clock Module (CKM)
    6. 8.6  DMA_B
    7. 8.7  Events
    8. 8.8  Memory
      1. 8.8.1 Memory Organization
      2. 8.8.2 Peripheral File Map
      3. 8.8.3 Peripheral Interrupt Vector
    9. 8.9  Flash Memory
    10. 8.10 SRAM
    11. 8.11 GPIO
    12. 8.12 IOMUX
    13. 8.13 ADC
    14. 8.14 Temperature Sensor
    15. 8.15 VREF
    16. 8.16 CRC
    17. 8.17 UART
    18. 8.18 SPI
    19. 8.19 I2C
    20. 8.20 Low-Frequency Sub System (LFSS)
    21. 8.21 RTC_B
    22. 8.22 IWDT_B
    23. 8.23 WWDT
    24. 8.24 Timers (TIMx)
    25. 8.25 Device Analog Connections
    26. 8.26 Input/Output Diagrams
    27. 8.27 Serial Wire Debug Interface
    28. 8.28 Device Factory Constants
    29. 8.29 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.6 DMA_B

The direct memory access (DMA) controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA can be used to move data from ADC conversion memory to SRAM. The DMA reduces system power consumption by allowing the CPU to remain in low power mode, without having to awaken to move data to or from a peripheral.

The DMA_B in these devices support the following key features:

  • 3 DMA transfer channel
    • 2 full-feature channels, supporting repeated transfer modes
    • 1 basic channel, supporting single transfer mode
  • Configurable DMA channel priorities
  • Direct peripheral to DMA trigger is supported from ADC, UART, SPI or timer triggers.
  • Byte (8-bit), short word (16-bit) and word (32-bit) or mixed byte and word transfer capability
  • Transfer counter block size supports up to 64k transfers of any data type
  • Configurable DMA transfer trigger selection
  • Active channel interruption to service other channels
  • Early interrupt generation for ping-pong buffer architecture
  • Cascading channels upon completion of activity on another channel
  • Stride mode to support data re-organization, such as 3-phase metering applications
  • Gather mode

DMA_B Channel Features shows the DMA features that are supported and the corresponding DMA channel numbers.
Table 8-2 DMA_B Channel Features
DMA Feature DMA_B
Full-Feature Channel Basic Channel
Channel Number 0, 1 2
Repeated mode ✓ –
Table & fill mode ✓ –
Gather mode ✓ –
Early IRQ notification ✓ –
Auto enable ✓ ✓
Long long (128-bit) transfer ✓ ✓
Stride mode ✓ ✓
Cascading channel support ✓ ✓
DMA Trigger Mapping lists the available triggers for the DMA which are configured using the DMATCTL.DMATSEL control bits in the DMA memory mapped registers.
Table 8-3 DMA Trigger Mapping
DMACTL.DMATSEL TRIGGER SOURCE
0 Software
1 Generic Subscriber 0 (FSUB_0)
2 Generic Subscriber 0 (FSUB_1)
9 UART0 PUBLISHER 1
10 UART0 PUBLISHER 2
13 UART2 PUBLISHER 1
14 UART2 PUBLISHER 2
7 SPI0 PUBLISHER 1
8 SPI0 PUBLISHER 2
5 I2C1 PUBLISHER 1
6 I2C1 PUBLISHER 2
3 I2C0 PUBLISHER 1
4 I2C0 PUBLISHER 2
15 ADC0 EVT g
11 UART1 PUBLISHER 1
12 UART1 PUBLISHER 2