SLASFE0 July   2025 MSPM0H3216-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes (PT, RUK, RGZ, RHB, DGS32, DGS28, RGE, DGS20 Packages)
    3. 6.3 Signal Descriptions
      1.      11
      2.      12
      3.      13
      4.      14
      5.      15
      6.      16
      7.      17
      8.      18
      9.      19
      10.      20
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Thermal Information
    4. 7.4  Supply Current Characteristics
      1. 7.4.1 RUN/SLEEP Modes
      2. 7.4.2 STOP/STANDBY Modes
    5. 7.5  Power Supply Sequencing
      1. 7.5.1 POR and BOR
      2. 7.5.2 Power Supply Ramp
    6. 7.6  Flash Memory Characteristics
    7. 7.7  Timing Characteristics
    8. 7.8  Clock Specifications
      1. 7.8.1 System Oscillator (SYSOSC)
      2. 7.8.2 Low Frequency Oscillator (LFOSC)
      3. 7.8.3 High Frequency Crystal/Clock
      4. 7.8.4 Low Frequency Crystal/Clock
    9. 7.9  Digital IO
      1. 7.9.1  Electrical Characteristics
      2. 7.9.2 Switching Characteristics
    10. 7.10 ADC
      1. 7.10.1 Electrical Characteristics
      2. 7.10.2 Switching Characteristics
      3. 7.10.3 Linearity Parameters
      4. 7.10.4 Typical Connection Diagram
    11. 7.11 Temperature Sensor
    12. 7.12 VREF
      1. 7.12.1 Voltage Characteristics
      2. 7.12.2 Electrical Characteristics
    13. 7.13 I2C
      1. 7.13.1 I2C Characteristics
      2. 7.13.2 I2C Filter
      3. 7.13.3 I2C Timing Diagram
    14. 7.14 SPI
      1. 7.14.1 SPI
      2. 7.14.2 SPI Timing Diagram
    15. 7.15 UART
    16. 7.16 TIMx
    17. 7.17 Windowed Watchdog Characteristics
    18. 7.18 Emulation and Debug
      1. 7.18.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  Overview
    2. 8.2  CPU
    3. 8.3  Operating Modes
      1. 8.3.1 Functionality by Operating Mode (MSPM0H321x)
    4. 8.4  Power Management Unit (PMU)
    5. 8.5  Clock Module (CKM)
    6. 8.6  DMA_B
    7. 8.7  Events
    8. 8.8  Memory
      1. 8.8.1 Memory Organization
      2. 8.8.2 Peripheral File Map
      3. 8.8.3 Peripheral Interrupt Vector
    9. 8.9  Flash Memory
    10. 8.10 SRAM
    11. 8.11 GPIO
    12. 8.12 IOMUX
    13. 8.13 ADC
    14. 8.14 Temperature Sensor
    15. 8.15 VREF
    16. 8.16 CRC
    17. 8.17 UART
    18. 8.18 SPI
    19. 8.19 I2C
    20. 8.20 Low-Frequency Sub System (LFSS)
    21. 8.21 RTC_B
    22. 8.22 IWDT_B
    23. 8.23 WWDT
    24. 8.24 Timers (TIMx)
    25. 8.25 Device Analog Connections
    26. 8.26 Input/Output Diagrams
    27. 8.27 Serial Wire Debug Interface
    28. 8.28 Device Factory Constants
    29. 8.29 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.3.1 Functionality by Operating Mode (MSPM0H321x)

Table 8-1 lists the supported functionality in each operating mode.

Functional key:

  • EN: The function is enabled in the specified mode.
  • DIS: The function is disabled (either clock or power gated) in the specified mode, but the function's configuration is retained.
  • OPT: The function is optional in the specified mode, and remains enabled if configured to be enabled.
  • NS: The function is not automatically disabled in the specified mode, but it is not supported.
  • OFF: The function is fully powered off in the specified mode, and no configuration information is retained.
Table 8-1 Supported Functionality by Operating Mode
Operating ModeRUNSLEEPSTOPSTANDBY
RUN0RUN1RUN2SLEEP0SLEEP1SLEEP2STOP0STOP2STANDBY0STANDBY1
OscillatorsSYSOSCENENDISENENDISOPT(1)DISDISDIS
LFOSCEN
ClocksCPUCLK32M32k32kDIS
MCLK to PD132M32k32k32M32k32kDIS
ULPCLK to PD032M32k32k32M32k32k4M(1)32kDIS
ULPCLK to TIMG14, TIMG832M32k32k32M32k32k4M(1)32k
MFCLKOPTDISOPTDISOPTDIS
LFCLK32kDIS
LFCLK to TIMG14, TIMG1,TIMG2,TIMG8, TIMA032k
MCLK MonitorOPTDIS
LFCLK MonitorOPT
PMUPOR MonitorEN
BOR MonitorEN
Core RegulatorFull driveLow drive
Core FunctionsCPUENDIS
DMAOPTNS (triggers supported)
FlashENOPTDIS
SRAMENOPTDIS
PD1 PeripheralsSPI0OPTDIS
CRCOPTDIS
PD0 PeripheralsTIMG14OPT
TIMG1OPTDIS
TIMG2OPTDIS
TIMG8OPTDIS
TIMA0OPTDIS
UART0OPTDIS
UART1OPTDIS
UART2OPTDIS
I2C0OPTDIS
I2C1OPTDIS
GPIOAOPTOPT(2)
GPIOBOPTOPT(2)
WWDT0OPTOPT(2)
AnalogADC0OPTNS (triggers supported)
VREFOPTNS
Temperature Sensor OPT OFF
IOMUX and IO WakeupEN
Wake SourcesN/AANY IRQPD0 IRQ
(1) If STOP0 is entered from RUN1 (SYSOSC enabled but MCLK sourced from LFCLK), SYSOSC remains enabled as it was in RUN1, and ULPCLK remains at 32kHz as it was in RUN1. If STOP0 is entered from RUN2 (SYSOSC was disabled and MCLK was sourced from LFCLK), SYSOSC remains disabled as it was in RUN2, and ULPCLK remains at 32kHz as it was in RUN2.
(2) When using the STANDBY1 policy for STANDBY, only TIMG14 is clocked. These PD0 peripherals can generate an asynchronous fast clock request upon external activity but are not actively clocked.