SLASFI0 July   2026 TMUXHS5212

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 High-Speed Performance Parameters
    7. 5.7 Switching Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Enable and Power Savings
      2. 6.3.2 Data Line Biasing
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 USB 3.2/4 Implementation for USB Type-C
    3. 7.3 Systems Examples
      1. 7.3.1 USB4 / TBT 3.0 Demuxing
      2. 7.3.2 DisplayPort Main Link Mux/Demux
      3. 7.3.3 MIPI Camera Serial Interface
    4. 7.4 PCIe Lane Muxing
      1. 7.4.1 Application Curves
    5. 7.5 Power Supply Recommendations
    6. 7.6 Layout
      1. 7.6.1 Layout Guidelines
      2. 7.6.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.4 PCIe Lane Muxing

The TMUXHS5212 can be used to switch PCIe lanes between two slots. In many PC and server motherboards, the CPU does not have enough PCIe lanes to provide desired system flexibility for end customers. In such applications, the TMUXHS5212 can be used to switch PCIe TX and RX lanes between two slots. Figure 7-6 provides a schematic where eight TMUXHS5212 devices are used to switch eight PCIe TX and eight RX lanes. Note: the common mode voltage (CMV) bias for the TMUXHS5212 must be within the range of 0 – 1.2V. In implementations where receiver CMV bias of a PCIe root complex or an end point cannot be ensured within the CMV range, additional DC blocking capacitors and appropriate CMV biasing must be implemented.

TMUXHS5212 PCIe Lane Muxing Figure 7-6 PCIe Lane Muxing