SLAU358Q September 2011 – October 2019
LONG MSPGANG_SetConfig(LONG index, LONG data)
Arguments
| LONG index | Configuration index. See list below. |
| LONG data | Configuration data |
Result
| LONG | Error code |
Syntax
LONG MSPGANG_GetConfig(LONG index)
Arguments
| LONG index | Configuration index. See list below. |
Result
| LONG data | Configuration data |
List of Indexes
#define FROMIMAGE_BIT 0x1000
#define CFG_INTERFACE 0
#define INTERFACE_NONE 0
#define INTERFACE_JTAG 4
#define INTERFACE_SBW 8
#define INTERFACE_BSL 0xC
#define INTERFACE_TYPE_MAX_INDEX INTERFACE_BSL
#define CFG_JTAG_SPEED 1
#define INTERFACE_FAST 0
#define INTERFACE_MED 1
#define INTERFACE_SLOW 2
#define INTERFACE_SPEED_MAX_INDEX INTERFACE_SLOW
#define CFG_SBW_SPEED 2
// INTERFACE_FAST 0
// INTERFACE_MED 1
// INTERFACE_SLOW 2
#define CFG_BSL_SPEED 3
// INTERFACE_FAST 0
// INTERFACE_MED 1
// INTERFACE_SLOW 2
#define CFG_IO_INTERFACE 4
#define SBW_VIA_TDOI_BIT 0x00
#define SBW_VIA_RST_BIT 0x01
// 0 - SBW_VIA_TDOI (pin 1) and TCK/TEST (pin-7/8)
// 1 - SBW_VIA_RST (pin 11) and TCK/TEST (pin-7/8)
#define CFG_POWERTARGETEN 6
#define EXTERNAL_POWER_WHOLE_RANGE 0 // external power supply - whole range from Vccmin to Vccmax
#define POWER_SUPPLIED_BY_MSPGANG 1 // targets supplied by MSP-GANG
#define EXTERNAL_POWER_IN_RANGE 2 // external power supply - verified range - selected Vcc +/- 0.3V
#define CFG_VCCINDEX 7
// Vcc in mV 1800 - 3600
#define CFG_ICC_HI_EN 8
// disable 0 (up to 30mA from MSP-GANG to each targets)
// enable 1 (up to 50mA from MSP-GANG to each targets)
#define CFG_BLOWFUSE 9
// disable 0
// enable 1
#define CFG_TARGET_EN_INDEX 10
// Targets GANG enable mask - 0x00 ...0xFF. Enable all targets -> 0xFF
#define TARGET_1_MASK 0x01
#define TARGET_2_MASK 0x02
#define TARGET_3_MASK 0x04
#define TARGET_4_MASK 0x08
#define TARGET_5_MASK 0x10
#define TARGET_6_MASK 0x20
#define TARGET_7_MASK 0x40
#define TARGET_8_MASK 0x80
#define CFG_FLASHERASEMODE 11
#define ERASE_NONE_MEM_INDEX 0
#define ERASE_ALL_MEM_INDEX 1
#define ERASE_PRG_ONLY_MEM_INDEX 2
#define ERASE_INFILE_MEM_INDEX 3
#define ERASE_DEF_CM_INDEX 4
#define ERASE_MAX_INDEX ERASE_DEF_CM_INDEX
#define CFG_ERASEINFOA 12 \
// disable 0
// enable 1
#define CFG_ERASEINFOB 13
// disable 0
// enable 1
#define CFG_ERASEINFOC 14
// disable 0
// enable 1
#define CFG_ERASEINFOD 15
// disable 0
// enable 1
#define CFG_MASSERASE_AND_INFOA_EN 16
// disable 0
// enable 1
#define CFG_ERASESTARTADDR 17
// FLASH/FRAM start erase address
#define CFG_ERASESTOPADDR 18
// FLASH/FRAM end erase address
#define CFG_FLASHREADMODE 19
#define READ_ALL_MEM_INDEX 0
#define READ_PRGMEM_ONLY_INDEX 1
#define READ_INFOMEM_ONLY_INDEX 2
#define READ_DEF_MEM_INDEX 3
#define READ_MEM_MAX_INDEX READ_DEF_MEM_INDEX
#define CFG_READINFOA 20
// disable 0
// enable 1
#define CFG_READINFOB 21
// disable 0
// enable 1
#define CFG_READINFOC 22
// disable 0
// enable 1
#define CFG_READINFOD 23
// disable 0
// enable 1
#define CFG_FINALACTION_MODE 24
#define APPLICATION_NO_RESET 0
#define APPLICATION_TOGGLE_RESET 1
#define APPLICATION_TOGGLE_VCC 2
#define APPLICATION_JTAG_RESET 3
#define APPLICATION_RESET_MAX_INDEX APPLICATION_JTAG_RESET
#define CFG_BEEPMODE 25
// sum of following bits
#define BEEP_PCSPK_EN_BIT 1 //Beep via PC Speaker enable
#define BEEP_OK_EN_BIT 2 //Beep when OK enable
#define BEEP_SOUND_EN_BIT 4 //Sound enable
#define CFG_DEFERASEMAINEN 26
// disable 0
// enable 1
#define CFG_CUSTOMRESETPULSETIME 27
// time in ms 1.....2000
#define CFG_CUSTOMRESETIDLETIME 28
// time in ms 1.....2000
#define CFG_BSL_ENH_ENABLE 29
// disable 0
// enable 1
#define CFG_BSL_ENH_INDEX 30
//for future usage
#define BSL_ENH_DISABLE 0
#define BSL_ENH_NONE 1
#define BSL_ENH_ERASE 2
#define BSL_ENH_MAX_INDEX 2
#define CFG_RETAIN_CAL_DATA_INDEX 31
// disable 0
// enable 1
#define CFG_FINALACTIONRUNTIME 32
// 0 - infinite,
// 1...120 time in seconds
#define CFG_FINALACTIONVCCOFFTIME 33
// Vcc-OFF (then again ON) time after programming when the
// APPLICATION_TOGGLE_VCC option is selected.
#define CFG_DCO_CONST_2XX_VERIFY_EN 35
// disable 0
// enable 1
#define CFG_DCOCAL_2XX_EN 36
// disable 0
// enable 1
#define CFG_BSL_FLASH_WR_EN 37
// mask for 4 BSL segments - disable->0, enable->1
// bit 0 -> 0x01 BSL segment 1
// bit 1 -> 0x02 BSL segment 2
// bit 2 -> 0x04 BSL segment 3
// bit 3 -> 0x08 BSL segment 4
#define CFG_BSL_FLASH_RD_EN 38
// mask for 4 BSL segments - disable->0, enable->1
// bit 0 -> 0x01 BSL segment 1
// bit 1 -> 0x02 BSL segment 2
// bit 2 -> 0x04 BSL segment 3
// bit 3 -> 0x08 BSL segment 4
#define CFG_READMAINMEMEN 39
// disable 0
// enable 1
#define CFG_READDEFSTARTADDR 40
// Memory READ start address
#define CFG_READDEFSTOPADDR 41
// Memory READ end address
#define CFG_COMPORT_NO 42
// Communication COM Port number - 0..255
#define CFG_UART_SPEED 43
// Baud Rate index
#define UART_9600 0
#define UART_19200 1
#define UART_38400 2
#define UART_57600 3
#define UART_115200 4
#define CFG_OPEN_FILE_TYPE 44
#define CODE_FILE_INDEX 0
#define APPEND_FILE_INDEX 1
#define PASSW_FILE_INDEX 2
#define SECONDCODE_FILE_INDEX 3
#define CODE2_FILE_INDEX 4
#define CFG_USE_SCRIPT_FILE 45
// disable 0
// enable 1
#define CFG_IMAGE_NO 46
//image number - 0...9
#define CFG_RESETTIME 47
#define RESET_10MS_INDEX 0
#define RESET_100MS_INDEX 1
#define RESET_200MS_INDEX 2
#define RESET_500MS_INDEX 3
#define RESET_CUSTOM_INDEX 4
#define RESET_MAX_INDEX RESET_CUSTOM_INDEX
#define CFG_PROJECT_SOURCE 48
#define INTERACTIVE_MODE 0
#define FROM_IMAGE_MEMORY_MODE 1
#define STANDALONE_MODE 2
#define FROM_IMAGE_FILE_MODE 3
#define PROJECT_SOURCE_MAX_INDEX FROM_IMAGE_FILE_MODE
#define CFG_COPY_CFG_FROM_MEMORY_EN 49
// Direct (eg. Interactive) 0
// From Image memory 1
#define CFG_RUNNING_SCRIPT_MODE 50
#define RUNNING_SCRIPT_NONE 0
#define RUNNING_SCRIPT_ONLINE 1
#define RUNNING_SCRIPT_OFFLINE 2
#define CFG_VCC_SETTLE_TIME 51
// Vss settle time in step 20 ms. Range 0...200 ( time 0...4000 ms)
#define CFG_JTAG_UNLOCK_EN 52
// disable 0
// enable 1
#define CFG_CODE2_FILE_EN 53
// disable 0
// enable 1
#define CFG_BSL_FIRST_PASSWORD 54
#define BSL_ANY_PASSW 0
#define BSL_PASSW_FROM_CODE_FILE 1
#define BSL_PASSW_FROM_PASSWORD_FILE 2
#define BSL_EMPTY_PASSW 3
#define CFG_DEFINED_RETAIN_DATA_EN 55
// disable 0
// enable 1
#define CFG_DEFINED_RETAIN_START_ADDR 56
//address must be even
#define CFG_DEFINED_RETAIN_END_ADDR 57
//address must be odd
#define DEFINED_RETAIN_DATA_MAX_SIZE 0x40
// END_ADDR - START_ADDR + 1 <= DEFINED_RETAIN_DATA_MAX_SIZE
#define CFG_SECURE_CODE_SOURCE 58
enum {USER_SOURCE=0, FILE_SOURCE=1};
#define CFG_MSP432_CLR_LOCKING_OPTIONS 59
#define MSP432_CLR_LOCKING_INFOA_BIT 0x01
#define MSP432_CLR_LOCKING_BSL_BIT 0x02
#define MSP432_CLR_LOCKING_MASK ( MSP432_CLR_LOCKING_INFOA_BIT | MSP432_CLR_LOCKING_BSL_BIT )
#define CFG_WRDEF_EXCLUDE_SECTIONS 60
// mask for 4 Read_Defined excluded sections disable->0, enable->1
// bit 0 -> 0x01 section 1
// bit 1 -> 0x02 section 2
// bit 2 -> 0x04 section 3
// bit 3 -> 0x08 section 4
#define CFG_RDDEF_EXCLUDE_SECTIONS 61
// mask for 4 Read_Defined excluded sections disable->0, enable->1
// bit 0 -> 0x01 section 1
// bit 1 -> 0x02 section 2
// bit 2 -> 0x04 section 3
// bit 3 -> 0x08 section 4
#define CFG_WRDEF_EXCLUDE_S1_START_ADDR 62
#define CFG_WRDEF_EXCLUDE_S1_END_ADDR 63
#define CFG_WRDEF_EXCLUDE_S2_START_ADDR 64
#define CFG_WRDEF_EXCLUDE_S2_END_ADDR 65
#define CFG_WRDEF_EXCLUDE_S3_START_ADDR 66
#define CFG_WRDEF_EXCLUDE_S3_END_ADDR 67
#define CFG_WRDEF_EXCLUDE_S4_START_ADDR 68
#define CFG_WRDEF_EXCLUDE_S4_END_ADDR 69
#define CFG_RDDEF_EXCLUDE_S1_START_ADDR 70
#define CFG_RDDEF_EXCLUDE_S1_END_ADDR 71
#define CFG_RDDEF_EXCLUDE_S2_START_ADDR 72
#define CFG_RDDEF_EXCLUDE_S2_END_ADDR 73
#define CFG_RDDEF_EXCLUDE_S3_START_ADDR 74
#define CFG_RDDEF_EXCLUDE_S3_END_ADDR 75
#define CFG_RDDEF_EXCLUDE_S4_START_ADDR 76
#define CFG_RDDEF_EXCLUDE_S4_END_ADDR 77
#define CFG_RD_TLV_EN 78
#define CFG_SERIALIZATION_EN 80
// disable 0
// enable 1
#define CFG_SN_ADDRESS_IN_MEMORY 81
//address must be even
#define CFG_SN_DATA_SIZE_IN_BYTES 82
//Size must be even 2...16
#define SN_DATA_MAX_SIZE 16
#define CFG_SN_REMOVE_CODE_FROM_SN_LOCATION 83
// disable 0
// enable 1
#define CFG_SN_SOURCE 84
#define SN_SOURCE_DEFINED 0
#define SN_SOURCE_FROM_FILE 1
// 0 - defined
// 1 - from file
#define CFG_SN_FORMAT_IN_MEMORY 85
#define SN_FORMAT_LSB_FIRST 0
#define SN_FORMAT_MSB_FIRST 1
#define CFG_SN_DATA_INCREMENT 86
#define CFG_INIT_SN_DATA_0 87
//Bits 0-31 of the SN init data
#define CFG_INIT_SN_DATA_1 (CFG_INIT_SN_DATA_0+1)
//Bits 32-63 of the SN init data
#define CFG_INIT_SN_DATA_2 (CFG_INIT_SN_DATA_0+2)
//Bits 64-91 of the SN init data
#define CFG_INIT_SN_DATA_3 (CFG_INIT_SN_DATA_0+3)
//Bits 92-127 of the SN init data
#define CFG_SN_DESTINATION 91
#define NUMBER_TO_FLASH 0
#define NUMBER_TO_MAC_REG 1
#define CFG_MPU_IPE_WR_LOCKED 92
// disable 0
// enable 1
#define CFG_MPU_IPE_WR_UNLOCKED 93
// disable 0
// enable 1
#define CFG_MPU_IPE_RD_UNLOCKED 94
// disable 0
// enable 1
#define CFG_MPU_IPE_START_ADDR 95
#define CFG_MPU_IPE_END_ADDR 96
#define CFG_ADDITIONAL_COMPORT_NO 200
// 0 - disable (default)
// 1-255 added COM port number 1-255
// MSP432P protection configuration
#define CFG_MSP432_MB_CMD 300
#define CFG_MSP432_MB_JTAG_SWD_LOCK_SECEN 301
#define CFG_MSP432_MB_JTAG_SWD_LOCK_AES_INIT_VECT0 302
#define CFG_MSP432_MB_JTAG_SWD_LOCK_AES_INIT_VECT1 303
#define CFG_MSP432_MB_JTAG_SWD_LOCK_AES_INIT_VECT2 304
#define CFG_MSP432_MB_JTAG_SWD_LOCK_AES_INIT_VECT3 305
#define CFG_MSP432_MB_JTAG_SWD_LOCK_AES_SECKEYS0 306
#define CFG_MSP432_MB_JTAG_SWD_LOCK_AES_SECKEYS1 307
#define CFG_MSP432_MB_JTAG_SWD_LOCK_AES_SECKEYS2 308
#define CFG_MSP432_MB_JTAG_SWD_LOCK_AES_SECKEYS3 309
#define CFG_MSP432_MB_JTAG_SWD_LOCK_AES_SECKEYS4 310
#define CFG_MSP432_MB_JTAG_SWD_LOCK_AES_SECKEYS5 311
#define CFG_MSP432_MB_JTAG_SWD_LOCK_AES_SECKEYS6 312
#define CFG_MSP432_MB_JTAG_SWD_LOCK_AES_SECKEYS7 313
#define CFG_MSP432_MB_JTAG_SWD_LOCK_UNENC_PWD0 314
#define CFG_MSP432_MB_JTAG_SWD_LOCK_UNENC_PWD1 315
#define CFG_MSP432_MB_JTAG_SWD_LOCK_UNENC_PWD2 316
#define CFG_MSP432_MB_JTAG_SWD_LOCK_UNENC_PWD3 317
#define CFG_MSP432_MB_SEC_ZONE0_SECEN 318
#define CFG_MSP432_MB_SEC_ZONE0_START_ADDR 319
#define CFG_MSP432_MB_SEC_ZONE0_LENGTH 320
#define CFG_MSP432_MB_SEC_ZONE0_AESINIT_VECT0 321
#define CFG_MSP432_MB_SEC_ZONE0_AESINIT_VECT1 322
#define CFG_MSP432_MB_SEC_ZONE0_AESINIT_VECT2 323
#define CFG_MSP432_MB_SEC_ZONE0_AESINIT_VECT3 324
#define CFG_MSP432_MB_SEC_ZONE0_SECKEYS0 325
#define CFG_MSP432_MB_SEC_ZONE0_SECKEYS1 326
#define CFG_MSP432_MB_SEC_ZONE0_SECKEYS2 327
#define CFG_MSP432_MB_SEC_ZONE0_SECKEYS3 328
#define CFG_MSP432_MB_SEC_ZONE0_SECKEYS4 329
#define CFG_MSP432_MB_SEC_ZONE0_SECKEYS5 330
#define CFG_MSP432_MB_SEC_ZONE0_SECKEYS6 331
#define CFG_MSP432_MB_SEC_ZONE0_SECKEYS7 332
#define CFG_MSP432_MB_SEC_ZONE0_UNENC_PWD0 333
#define CFG_MSP432_MB_SEC_ZONE0_UNENC_PWD1 334
#define CFG_MSP432_MB_SEC_ZONE0_UNENC_PWD2 335
#define CFG_MSP432_MB_SEC_ZONE0_UNENC_PWD3 336
#define CFG_MSP432_MB_SEC_ZONE0_ENCUPDATE_EN 337
#define CFG_MSP432_MB_SEC_ZONE0_DATA_EN 338
#define CFG_MSP432_MB_SEC_ZONE1_SECEN 339
#define CFG_MSP432_MB_SEC_ZONE1_START_ADDR 340
#define CFG_MSP432_MB_SEC_ZONE1_LENGTH 341
#define CFG_MSP432_MB_SEC_ZONE1_AESINIT_VECT0 342
#define CFG_MSP432_MB_SEC_ZONE1_AESINIT_VECT1 343
#define CFG_MSP432_MB_SEC_ZONE1_AESINIT_VECT2 344
#define CFG_MSP432_MB_SEC_ZONE1_AESINIT_VECT3 345
#define CFG_MSP432_MB_SEC_ZONE1_SECKEYS0 346
#define CFG_MSP432_MB_SEC_ZONE1_SECKEYS1 347
#define CFG_MSP432_MB_SEC_ZONE1_SECKEYS2 348
#define CFG_MSP432_MB_SEC_ZONE1_SECKEYS3 349
#define CFG_MSP432_MB_SEC_ZONE1_SECKEYS4 350
#define CFG_MSP432_MB_SEC_ZONE1_SECKEYS5 351
#define CFG_MSP432_MB_SEC_ZONE1_SECKEYS6 352
#define CFG_MSP432_MB_SEC_ZONE1_SECKEYS7 353
#define CFG_MSP432_MB_SEC_ZONE1_UNENC_PWD0 354
#define CFG_MSP432_MB_SEC_ZONE1_UNENC_PWD1 355
#define CFG_MSP432_MB_SEC_ZONE1_UNENC_PWD2 356
#define CFG_MSP432_MB_SEC_ZONE1_UNENC_PWD3 357
#define CFG_MSP432_MB_SEC_ZONE1_ENCUPDATE_EN 358
#define CFG_MSP432_MB_SEC_ZONE1_DATA_EN 359
#define CFG_MSP432_MB_SEC_ZONE2_SECEN 360
#define CFG_MSP432_MB_SEC_ZONE2_START_ADDR 361
#define CFG_MSP432_MB_SEC_ZONE2_LENGTH 362
#define CFG_MSP432_MB_SEC_ZONE2_AESINIT_VECT0 363
#define CFG_MSP432_MB_SEC_ZONE2_AESINIT_VECT1 364
#define CFG_MSP432_MB_SEC_ZONE2_AESINIT_VECT2 365
#define CFG_MSP432_MB_SEC_ZONE2_AESINIT_VECT3 366
#define CFG_MSP432_MB_SEC_ZONE2_SECKEYS0 367
#define CFG_MSP432_MB_SEC_ZONE2_SECKEYS1 368
#define CFG_MSP432_MB_SEC_ZONE2_SECKEYS2 369
#define CFG_MSP432_MB_SEC_ZONE2_SECKEYS3 370
#define CFG_MSP432_MB_SEC_ZONE2_SECKEYS4 371
#define CFG_MSP432_MB_SEC_ZONE2_SECKEYS5 372
#define CFG_MSP432_MB_SEC_ZONE2_SECKEYS6 373
#define CFG_MSP432_MB_SEC_ZONE2_SECKEYS7 374
#define CFG_MSP432_MB_SEC_ZONE2_UNENC_PWD0 375
#define CFG_MSP432_MB_SEC_ZONE2_UNENC_PWD1 376
#define CFG_MSP432_MB_SEC_ZONE2_UNENC_PWD2 377
#define CFG_MSP432_MB_SEC_ZONE2_UNENC_PWD3 378
#define CFG_MSP432_MB_SEC_ZONE2_ENCUPDATE_EN 379
#define CFG_MSP432_MB_SEC_ZONE2_DATA_EN 380
#define CFG_MSP432_MB_SEC_ZONE3_SECEN 381
#define CFG_MSP432_MB_SEC_ZONE3_START_ADDR 382
#define CFG_MSP432_MB_SEC_ZONE3_LENGTH 383
#define CFG_MSP432_MB_SEC_ZONE3_AESINIT_VECT0 384
#define CFG_MSP432_MB_SEC_ZONE3_AESINIT_VECT1 385
#define CFG_MSP432_MB_SEC_ZONE3_AESINIT_VECT2 386
#define CFG_MSP432_MB_SEC_ZONE3_AESINIT_VECT3 387
#define CFG_MSP432_MB_SEC_ZONE3_SECKEYS0 388
#define CFG_MSP432_MB_SEC_ZONE3_SECKEYS1 389
#define CFG_MSP432_MB_SEC_ZONE3_SECKEYS2 390
#define CFG_MSP432_MB_SEC_ZONE3_SECKEYS3 391
#define CFG_MSP432_MB_SEC_ZONE3_SECKEYS4 392
#define CFG_MSP432_MB_SEC_ZONE3_SECKEYS5 393
#define CFG_MSP432_MB_SEC_ZONE3_SECKEYS6 394
#define CFG_MSP432_MB_SEC_ZONE3_SECKEYS7 395
#define CFG_MSP432_MB_SEC_ZONE3_UNENC_PWD0 396
#define CFG_MSP432_MB_SEC_ZONE3_UNENC_PWD1 397
#define CFG_MSP432_MB_SEC_ZONE3_UNENC_PWD2 398
#define CFG_MSP432_MB_SEC_ZONE3_UNENC_PWD3 399
#define CFG_MSP432_MB_SEC_ZONE3_ENCUPDATE_EN 400
#define CFG_MSP432_MB_SEC_ZONE3_DATA_EN 401
#define CFG_MSP432_MB_BSL_EABLE 402
#define CFG_MSP432_MB_BSL_START_ADDR 403
#define CFG_MSP432_MB_BSL_HARD_INV_PARAMS 404
#define CFG_MSP432_MB_JTAG_SWD_LOCK_ENCPAYLOADADDR 405
#define CFG_MSP432_MB_JTAG_SWD_LOCK_ENCPAYLOADLEN 406
#define CFG_MSP432_MB_JTAG_SWD_LOCK_DST_ADDR 407
#define CFG_MSP432_MB_SEC_ZONE0_PAYLOADADDR 408
#define CFG_MSP432_MB_SEC_ZONE0_PAYLOADLEN 409
#define CFG_MSP432_MB_SEC_ZONE1_PAYLOADADDR 410
#define CFG_MSP432_MB_SEC_ZONE1_PAYLOADLEN 411
#define CFG_MSP432_MB_SEC_ZONE2_PAYLOADADDR 412
#define CFG_MSP432_MB_SEC_ZONE2_PAYLOADLEN 413
#define CFG_MSP432_MB_SEC_ZONE3_PAYLOADADDR 414
#define CFG_MSP432_MB_SEC_ZONE3_PAYLOADLEN 415
#define CFG_MSP432_MB_FACTORY_RESET_ENABLE 416
#define CFG_MSP432_MB_FACTORY_RESET_PWDEN 417
#define CFG_MSP432_MB_FACTORY_RESET_PWD0 418
#define CFG_MSP432_MB_FACTORY_RESET_PWD1 419
#define CFG_MSP432_MB_FACTORY_RESET_PWD2 420
#define CFG_MSP432_MB_FACTORY_RESET_PWD3 421
#define CFG_MSP432_MB_FACTORY_RESET_PASSWORD0 422
#define CFG_MSP432_MB_FACTORY_RESET_PASSWORD1 423
#define CFG_MSP432_MB_FACTORY_RESET_PASSWORD2 424
#define CFG_MSP432_MB_FACTORY_RESET_PASSWORD3 425
// MSP432E protection configuration
#define CFG_MSP432E_FMPREADEN0_DATA 430
#define CFG_MSP432E_FMPREADEN1_DATA 431
#define CFG_MSP432E_FMPREADEN2_DATA 432
#define CFG_MSP432E_FMPREADEN3_DATA 433
#define CFG_MSP432E_FMPREADEN4_DATA 434
#define CFG_MSP432E_FMPREADEN5_DATA 435
#define CFG_MSP432E_FMPREADEN6_DATA 436
#define CFG_MSP432E_FMPREADEN7_DATA 437
#define CFG_MSP432E_FMPREADEN8_DATA 438
#define CFG_MSP432E_FMPREADEN9_DATA 439
#define CFG_MSP432E_FMPREADEN10_DATA 440
#define CFG_MSP432E_FMPREADEN11_DATA 441
#define CFG_MSP432E_FMPREADEN12_DATA 442
#define CFG_MSP432E_FMPREADEN13_DATA 443
#define CFG_MSP432E_FMPREADEN14_DATA 444
#define CFG_MSP432E_FMPREADEN15_DATA 445
#define CFG_MSP432E_FMPPRGEN0_DATA 446
#define CFG_MSP432E_FMPPRGEN1_DATA 447
#define CFG_MSP432E_FMPPRGEN2_DATA 448
#define CFG_MSP432E_FMPPRGEN3_DATA 449
#define CFG_MSP432E_FMPPRGEN4_DATA 450
#define CFG_MSP432E_FMPPRGEN5_DATA 451
#define CFG_MSP432E_FMPPRGEN6_DATA 452
#define CFG_MSP432E_FMPPRGEN7_DATA 453
#define CFG_MSP432E_FMPPRGEN8_DATA 454
#define CFG_MSP432E_FMPPRGEN9_DATA 455
#define CFG_MSP432E_FMPPRGEN10_DATA 456
#define CFG_MSP432E_FMPPRGEN11_DATA 457
#define CFG_MSP432E_FMPPRGEN12_DATA 458
#define CFG_MSP432E_FMPPRGEN13_DATA 459
#define CFG_MSP432E_FMPPRGEN14_DATA 460
#define CFG_MSP432E_FMPPRGEN15_DATA 461
#define CFG_MSP432E_USER_REG0 462
#define CFG_MSP432E_USER_REG1 463
#define CFG_MSP432E_USER_REG2 464
#define CFG_MSP432E_USER_REG3 465
#define CFG_MSP432E_USERDEBUGDATA 466
#define CFG_MSP432E_FP_REG_WREN 467
#define CFG_MSP432E_USER_REG_WREN 468
#define CFG_MSP432E_DBG_REG_WREN 469
#define CFG_MSP432E_PROTECTION_SOURCE 470