Connect a signal generator to the
DEVCLK input of the EVM through a bandpass filter. This signal generator must be
a low-noise signal generator. TI recommends a Trilithic-tunable bandpass filter
to filter the signal coming from the generator. Configure the signal generator
for the desired clock frequency in the range of 0.8 to 5.2 GHz. For best
performance when using an RF signal generator, the power input to the CLK SMA
connector must be 10 dBm (2.0 Vpp into 50 Ω). The signal generator must increase
above 10 dBm by an amount equal to any additional attenuation in the clock
signal path, such as the insertion loss of the bandpass filter. For example, if
the filter insertion loss is 2 dB, the signal generator must be set to 10 dBm +
2 dB = 12 dBm.
Connect a signal generator to the
reference signal input of the EVM at REF CLK(J17). Configure the signal
generator for the desired (260 MHz) clock frequency. Set the output power to
approximately 6–9 dBm.
Note:
The reference clock frequency can be obtained from
the ADC12DJ5200RFEVM GUI. Once the ADC12DJ5200EVM GUI is configured
to the desired JMODE mode and clock rate. The reference clock
frequency required by the EVM is displayed on the first page of the
GUI shown with red square in Figure 3-2
Ensure that the DEVCLK and reference clock sources
are frequency-locked using a common 10-MHz reference to ensure
functionality. Frequency locking the input signal generator to the
other generators can also be done if coherent sampling is
desired.
Do not turn on the RF output of any signal
generator at this time.
When using the ADC in single-input mode, the device
uses both edges of DEVCLK for sampling.