SLAU888 may   2023 AFE882H1

 

  1.   AFE882H1 Evaluation Module
  2.   Trademarks
  3. 1Overview
    1. 1.1 Kit Contents
    2. 1.2 Related Documentation From Texas Instruments
  4. 2System Setup
    1. 2.1 Software Setup
    2. 2.2 Hardware Setup
      1. 2.2.1 Electrostatic Discharge Caution
      2. 2.2.2 Power Configuration and Jumper Settings
      3. 2.2.3 Connecting the Hardware
        1. 2.2.3.1 Power Configuration
        2. 2.2.3.2 External SPI and UART Controllers
  5. 3Detailed Description
    1. 3.1 Hardware Description
      1. 3.1.1 Theory of Operation
      2. 3.1.2 Signal Definitions
      3. 3.1.3 XTR305 Configuration
    2. 3.2 Software Description
      1. 3.2.1 Starting the Software
      2. 3.2.2 Software Features
        1. 3.2.2.1 High Level Configuration Page
        2. 3.2.2.2 AFE882H1 Register Page
  6. 4Schematics, PCB Layout, and Bill of Materials
    1. 4.1 Board Schematic
    2. 4.2 PCB Components Layout
    3. 4.3 Bill of Materials

3.1.1 Theory of Operation

Figure 3-1 shows the block diagram of the AFE882H1EVM board. The AFE882H1 connects to a local machine USB port through a USB-A to Micro-USB cable.

GUID-20221013-SS0I-KZGG-LRFB-J9KNBZNMFMN3-low.svg Figure 3-1 Block Diagram for the AFE882H1EVM

With the default jumper settings, the USB sources a 3.3-V supply for PVDD and a 1.8-V supply for IOVDD. The PVDD and IOVDD supplies source power through J26 and J27, respectively. To use external supplies, remove the shunts connecting the jumpers and use the banana jack connectors at J22 for PVDD and J24 for IOVDD.

The output of the AFE882H1 sets the input voltage of an XTR305 current or voltage output driver. The XTR305 requires ±15-V supplies that are applied to banana jack connectors J7 and J8. With the resistor settings of the XTR305, the output can be set to a voltage range of ±11 V or a current range of –25-mA to +25-mA. Access the AFE882H1 output and XTR305 output at SMA connectors J11 and J12, respectively.

SMA connector J14 is coupled to the HART input of the AFE882H1. Jumpers at J4 and J6 determine if the HART signal is capacitively coupled to the device, or if the HART signal connects to the device through an external filter. Access the HART output at SMA connector J18. SMA connectors J10 and J13 connect to the inputs of a 16-bit ADC on the AFE882H1, and SMA connector J17 connects to the device CLK_OUT output clock.