SLAZ769 December   2025 MSPM33C321A

 

  1.   1
  2.   Abstract
  3. 1Functional Advisories
  4. 2Preprogrammed Software Advisories
  5. 3Debug Only Advisories
  6. 4Fixed by Compiler Advisories
  7. 5Device Nomenclature
    1. 5.1 Device Symbolization and Revision Identification
  8. 6Advisory Descriptions
    1. 6.1 AES_ERR_01
    2. 6.2 GPIO_ERR_05
    3. 6.3 GPIO_ERR_06
    4. 6.4 KEYSTORE_ERR_01
    5. 6.5 SYSCTL_ERR_01
    6. 6.6 SYSPLL_ERR_01
    7. 6.7 TIMER_ERR_04
    8. 6.8 TIMER_ERR_06
    9. 6.9 TIMER_ERR_07
  9. 7Trademarks
  10. 8Revision History

6.3 GPIO_ERR_06

GPIO Module

Category

Functional

Function

Writing to GPIO DOUT, DOUTSET and DOUTCLR registers might get missed when a DMA transfer is ongoing

Description

The GPIO DOUT, DOUTSET and DOUTCLR registers cannot be accessed by the DMA. Due to mistake in the implementation, the CPU access to the GPIO DOUT, DOUTSET and DOUTCLR will be also be blocked when a concurrent DMA transfer is in progress.

Workaround

In the application code, instead of writing to the DOUT, DOUTSET, and DOUTCLR registers, software should perform equivalent writes to the DOUTTGL register (see workaround GPIO_ERR_05 for restrictions on CPU writes to the DOUTTGL register).

In the pseudo code below, "pins" denotes the bit vector of pins in the GPIO module to be configured.

DL_GPIO_setPins(GPIO_Regs* gpio, uint32_t pins)
{    
    gpio->DOUTTGL31_0 = ~(gpio->DOUT31_0) & pins;
}

DL_GPIO_clearPins(GPIO_Regs* gpio, uint32_t pins)
{
    gpio->DOUTTGL31_0 = gpio->DOUT31_0 & pins;
}

DL_GPIO_writePins(GPIO_Regs* gpio, uint32_t pins)
{
    gpio->DOUTTGL31_0 = ~(gpio->DOUT31_0) & pins;
    gpio->DOUTTGL31_0 = gpio->DOUT31_0 & (~pins);
}

DL_GPIO_writePinsVal(GPIO_Regs* gpio, uint32_t pinsMask, uint32_t pinsVal)
{
    uint32_t doutVal = gpio->DOUT31_0;
    doutVal &= ~pinsMask;
    doutVal |= (pinsVal & pinsMask);
    gpio->DOUTTGL31_0 = ~(gpio->DOUT31_0) & doutVal;
    gpio->DOUTTGL31_0 = gpio->DOUT31_0 & (~doutVal);
}