SLLA565 September   2021 TUSB1044

 

  1.   Trademarks
  2. 1Introduction
  3. 2TUSB1044 Configuration and Control Implementation
    1. 2.1 TUSB1044 Four-Level Pins
      1. 2.1.1 I2C_EN
      2. 2.1.2 VIO_SEL
      3. 2.1.3 UEQ[1:0] and DEQ[1:0]
      4. 2.1.4 CFG[1:0]
    2. 2.2 TUSB1044 Two-Level Pins
      1. 2.2.1 FLIP, CTL0, and CTL1
      2. 2.2.2 DIR0 and DIR1
      3. 2.2.3 SWAP
      4. 2.2.4 HPDIN
      5. 2.2.5 SLP_S0#
  4. 3TUSB1044 I2C Mode Implementation
    1. 3.1 TUSB1044 Operating Mode Configuration, General_1 Register, 0x0A
    2. 3.2 VOD Configuration, General_3 Register 0x0C
    3. 3.3 Upstream and Downstream Equalization Configuration Registers, UFP1_EQ, UFP2_EQ, DFP1_EQ, and DFP2_EQ Registers 0x10, 0x11, 0x20, 0x21
  5. 4Benefits of Using the I2C Mode Control
  6. 5TUSB1044 Host Implementation Example
  7. 6TPS6598X, TPS6599X Based I2C Control and Tuning
    1. 6.1 Enable PD Controller I2C Control of External Slaves
    2. 6.2 Example of I2C Configuration Upon PD Controller PoR Event and Detach Event
    3. 6.3 Example of I2C Configuration Upon Cable-Orientation Event and DP Configuration Event
    4. 6.4 Notes for Application
  8. 7References

3.1 TUSB1044 Operating Mode Configuration, General_1 Register, 0x0A

Register 0x0A is the control interface switching the TUSB1044 USB, DP operation mode using bit [2:0]. Table 3-3 lists the bit definitions of register 0x0A. Bit [4] allows the EQ setting to be configured through I2C, overrides the default pin configuration.

Table 3-3 Register 0x0A Bit Definition
Bit Field Type Reset Description
7 RESERVED R 0h

Reserved
6 RESERVED R/W 0h

Reserved
5 SWAP_SEL R/W 0h

Setting this field performs a global direction swap on all the channels.

0h = Channel directions and EQ settings are in normal mode

1h = Reverse all channel directions and EQ settings for the input ports.
4 EQ_OVERRIDE R/W 0h

Setting this field will allow software to use EQ settings from registers instead of value sampled from pins.

0h = EQ settings based on sampled state of EQ pins.

1h = EQ settings based on programmed value of each of the EQ registers.
3 HPDIN_OVERRIDE R/W 0h

Overrides HPDIN pin state.

0h = HPD_IN based on HPD_IN pin.

1h = HPD_IN high.
2 FLIP_SEL R/W 0h

FLIPSEL

0h = Normal Orientation

1h = Flip orientation.
1-0 CTLSEL[1:0] R/W 1h

Controls the DP and USB modes.

0h = Disabled. All RX and TX for USB3 and DisplayPort are disabled.

1h = USB3.1 only enabled.

2h = Four Lanes of DisplayPort enabled.

3h = USB3.1 and Two DisplayPort Lanes.