As one of the more complicated operations on the TCAN24xx/TCAN28xx line of families this example can go through the procedure or setting up partial networking as well as optional options such as DLC and data validation in addition to standard ID verification. The terms partial networking and selective wake are used interchangeably throughout most documentation – these terms refer to the same thing. These steps must be followed exactly as stated or else partial networking/selective wake configuration can fail.

The main registers of concern are SBC_CONFIG (address Ch), CAN_CNTRL_1 (address 10h), SW_IDx (addresses 30h through 33h), SW_ID_MASKx (addresses 34h through 37h), SW_ID_MASK_DLC (address 38h), DATAx (addresses 39h through 40h), and SW_CONFIG_x (addresses 44h through 47h).

The high-level procedure is as follows:

1. Write all control registers for frame detection – this includes ID, ID_MASK, SW_ID_MASK_DLC, DATA, and SW_CONFIG registers; do not write 0b1 to bit 7 of SW_CONFIG_4 until step 3.
2. Read back all registers that were written to verify correct data exists within them
3. Set SWCFG (bit 7 of SW_CONFIG_4) to 0b1 when partial networking setup is complete.
4. Enable Selective wake in CAN_CNTRL_1 register (write a 0b1 into bit field 7 (MSB))
5. Set Device into standby mode regardless of current state (even if device is currently in standby mode).

For a straight example the most common setup is examined – which is enabling selective wake to only do ID verification – so DLC and data verification is not needed in this example. The setup assumes 11-bit IDs, that must match the following ID – 0b1100xxxxxxx (x = do not care) – for a selective wake to occur. The CAN Data rate is 125kbps, CAN FD frames are ignored for error counter, frame error counter threshold is set to 31 (frame overflow flag can be set on 32nd frame error). Using the guidelines previously mentioned the programming flow is as follows

1. Since we are working with classic 11-bit IDs SW_ID1 and SW_ID2 registers can be skipped over.
2. In SW_ID3 there are a few questions to answer
   1. Bits 7-6 are extended ID bits – so these can be kept at 0b00
   2. Bit 5 is the flag selecting Extended or Classic ID; since standard is used here this needs to be kept at default level of 0b0
   3. Bits 4-0 represent ID bits 10:6 – the 5 most significant bits of the ID; since we only care about the 4 most significant bits in this example either 0b11000 or 0b11001 needs to be written here
   4. So, to configure this register write 0x18 or 0x19 to address 32h
3. Next is SW_ID4 and there is only one main question here:
   1. Bits 7-2 represent ID bits 5:0 – the 6 least significant bits of the ID; since we have listed these as do not care the default value of 0b000000 can be kept and no further write is needed.
4. SW_ID_MASK1 through SW_ID_MASK3 only deal with extended ID bits and can be kept default for this example.
5. SW_ID_MASK4 does need to be used as this register controls which bits are do not care. The entire byte represents ID mask values for bits 10:3. A bit value of one in bit position n represents that the SBC needs to consider this a do not care while a bit value of 0 indicates that the SBC needs to care.
   1. Since only the 4 most significant bits are cared about the byte needs to be 0b00001111 or 0x0F
   2. To configure the register, write a value of 0x0F to address 37h.
6. The SW_ID_MASK_DLC register has multiple functions, this contains mask bits (positions 7:5), DLC code (positions 4:1), and the data mask enable. In this example DLC and data verification are not used and can be ignored.
   1. Since bits 7:5 contain mask data for bits 2:0 of a classic 11-bit ID and these values are do not care in this example and need to be written to with a bit pattern of 0b111 while the rest of the register is kept default (0b00000) – which results in data 0xE0.
   2. Write 0xE0 to register address 38h.
7. Since data matching is not enabled in this example all data registers (39h through 40h) can be kept with default configuration and skipped over
8. Next is SW_CONFIG_1 which has 3 configuration options: SW_FD_PASSIVE (bit 7) which modifies the error counters behavior upon the reception of a CAN FD frame – by default (0b0) and are counted as errors but setting to 0b1 can ignore CAN FD frames. Next is the CAN bus data rate which is in bit field 6:4 with 6 available options. Next there is the CAN FD data rate in bit field 3:2. Finally the last 2 bits are reserved.
   1. In the example CAN FD frames are ignored for error counter so that needs to be changed to 1.
   2. The CAN data rate is 125kbps which is the value 0b010
   3. The FD_DR bit field can be kept default in this example – so this can stay 0b00.
   4. To finalize this configuration, write 0xA0 to address 44h
9. SW_CONFIG_2 is a read only register this contains the frame error counter value – for configuration this register can be ignored.
10. SW_CONFIG_3 contains the frame error counter threshold; the default value is 31 which means the 32nd error can cause the frame overflow flag to be set. The example keeps the default value but this is able to be set from 0 to 255.
11. Read back all modified registers in the previous steps to make sure that the proper configuration has been input. This step isn’t required for functionality – but strongly encouraged.
12. SW_CONFIG_4 is the last register to configure as only bit 7 can be modified – bit 7 is the SWCFG bit which by default is 0b0 – when set to 0b1 the SBC has selective wake parameters configured. That means to finalize the configuration 0x80 needs to be written to address 47h. If any register between address 30h to 44h and address 46h are written to after this bit has been set this can automatically clear, this is also the case when a frame overflow error occurs.
13. Now with the partial networking configured, this needs to be enabled via the CAN_CNTRL_1 register. Assuming default condition (0x04) the correct bit pattern to write to address 10h is 0x84.
14. After partial networking has been enabled the device must be set to standby mode – this step must be done even if the device is already in standby mode. Assuming default conditions that means the data 0x86 (TCAN24xx devices) | 0x06 (TCAN28xx devices) needs to be written to address Ch.
15. Partial networking has been configured.