3 Register Organization

The TCAN28xx and TCAN24xx lines of devices are configurable through the register stack located within device. For a detailed list of registers and the respective bit fields please see Device Registers section in the data sheet. Most control of the device is done through the SPI bus while interacting with the host controller.

Each register is comprised of 1 byte and there is one register per address within the device. There are 5 register access types within this family of device; two read access types and three write access types. Read access is denoted by “R” denoting that this bit field can be read while a code “RH” indicates that the bit field is set or cleared upon reception of hardware read. Write access has three types where basic write access is denoted by “W”, a hardware writes “H”, and a write 1 to clear “W1C” access types. Each bit field described in register tables from data sheet can also stipulate the access code.

The register stack is largely sectioned off into five main groups that are grouped based on what features the groups are connected to. The first group is the ID and revision registers of the device and exists between register address 0h through 8h and contains the device ID (which essentially the part number) and the major and minor revision ID (which needs to be 2.1 for production material). After that the next group can be considered major device registers which last from address 9h through address Eh. These registers control the SPI configuration, power regulation options, and SBC control options – which are options that need to be considered for every single application whereas the rest of the configuration registers are only used if application demands a deviation in default configuration. The third category is debug – there is only one register in this group and that is at address Fh – which has no influence on the rest of the SBC’s operation and only acts as a test register that can be read and written to. This register is mainly used to confirm SPI reads and writes are working as expected without any impact the overall SBCs functionality. The next group of registers is the largest and this can be thought of as optional feature configuration registers which start at address 10h and through 4Fh – this includes all other configuration options that are not in the first “major” device function group including but not limited to transceiver configuration, watch dog timer, selective wake, and HSS control to name a few. Most of the configuration options can be programmed into this part of the register stack. Finally, the last group of registers starts at address 50h and goes through address 62h and this is where the interrupts and interrupt masks are stored within the register stack. Address 50h is the global interrupt vector - which is always sent out of the SDO pin for every SPI transaction as the first byte – this register monitors INT1 – INT4, INT_CANBUS, and INT6-INT7 where each interrupt register gets a bit in the global vector. The other registers contain the eight interrupt registers as well as enable masks for those interrupts in case certain interrupts want to be suppressed by the application.

That is the basic overview of the register stack – and the general categories in which the registers fall under.