SLLSEO5D October   2015  – March 2021 TUSB322I

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
  6. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Cables, Adapters, and Direct Connect Devices
        1. 6.3.1.1 USB Type-C Receptacles and Plugs
        2. 6.3.1.2 USB Type-C Cables
        3. 6.3.1.3 Legacy Cables and Adapters
        4. 6.3.1.4 Direct Connect Devices
        5. 6.3.1.5 Audio Adapters
      2. 6.3.2 Port Role Configuration
        1. 6.3.2.1 Downstream Facing Port (DFP) - Source
        2. 6.3.2.2 Upstream Facing Port (UFP) - Sink
        3. 6.3.2.3 Dual Role Port (DRP)
      3. 6.3.3 Type-C Current Mode
      4. 6.3.4 Accessory Support
        1. 6.3.4.1 Audio Accessory
        2. 6.3.4.2 Debug Accessory
      5. 6.3.5 I2C and GPIO Control
      6. 6.3.6 VBUS Detection
      7. 6.3.7 Cable Orientation and External MUX Control
      8. 6.3.8 VCONN Support for Active Cables
    4. 6.4 Device Functional Modes
      1. 6.4.1 Unattached Mode
      2. 6.4.2 Active Mode
      3. 6.4.3 Shutdown Mode
      4. 6.4.4 Dead Battery Mode
    5. 6.5 Programming
    6. 6.6 Register Maps
      1. 6.6.1 CSR Registers
        1. 6.6.1.1 Device Identification Register (offset = 0x07 through 0x00) [reset = 0x00, 0x54, 0x55, 0x53, 0x42, 0x33, 0x32, 0x32]
        2. 6.6.1.2 Connection Status Register (offset = 0x08) [reset = 0x00]
        3. 6.6.1.3 Connection Status and Control Register (offset = 0x09) [reset = 0x20]
        4. 6.6.1.4 General Control Register (offset = 0x0A) [reset = 0x00]
        5. 6.6.1.5 Device Revision Register (offset = 0xA0) [reset = 0x02]
  7. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 DRP in I2C Mode
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
      2. 7.2.2 DFP in I2C Mode
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Curves
      3. 7.2.3 UFP in I2C Mode
        1. 7.2.3.1 Design Requirements
        2. 7.2.3.2 Detailed Design Procedure
        3. 7.2.3.3 Application Curves
    3. 7.3 Initialization Set Up
  8. 8 Layout
    1. 8.1 Layout Guidelines
    2. 8.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Community Resources
    4. 9.4 Trademarks
  10. 10Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
Power Consumption
ISHUTDOWN_UFPLeakage current when VDD is supplied but the device is not enabled. (VDD = 5 V, EN_N = H)0.04µA
IUNATTACHED_UFPCurrent consumption in unattached mode when port is unconnected and waiting for connection. (VDD = 5 V, ADDR = NC, MODE_SELECT = 2'b01)70µA
IACTIVE_UFPCurrent consumption in active mode. (VDD = 5 V, ADDR = NC, MODE_SELECT = 2'b01)70µA
CC1 and CC2 Pins
RCC_DBPulldown resistor when in dead-battery mode.4.15.16.1kΩ
RCC_DPulldown resistor when in UFP or DRP mode.4.65.15.6kΩ
VUFP_CC_USBVoltage level range for detecting a DFP attach when configured as a UFP and DFP is advertising default current source capability.0.250.61V
VUFP_CC_MEDVoltage level range for detecting a DFP attach when configured as a UFP and DFP is advertising medium (1.5 A) current source capability.0.71.16V
VUFP_CC_HIGHVoltage level range for detecting a DFP attach when configured as a UFP and DFP is advertising high (3 A) current source capability.1.312.04V
VTH_DFP_CC_USBVoltage threshold for detecting a UFP attach when configured as a DFP and advertising default current source capability.1.511.61.64V
VTH_DFP_CC_MEDVoltage threshold for detecting a UFP attach when configured as a DFP and advertising medium current (1.5 A) source capability.1.511.61.64V
VTH_DFP_CC_HIGHVoltage threshold for detecting a UFP attach when configured as a DFP and advertising high current (3.0 A) source capability.2.462.62.74V
VTH_AC_CC_USBVoltage threshold for detecting a active cable attach when configured as a DFP and advertising default current source.0.150.20.25V
VTH_AC_CC_MEDVoltage threshold for detecting a active cable attach when configured as a DFP and advertising medium current (1.5 A) source.0.350.40.45V
VTH_AC_CC_HIGHVoltage threshold for detecting a active cable attach when configured as a DFP and advertising high current (3.0 A) source.0.760.80.84V
ICC_DEFAULT_PDefault mode pullup current source when operating in DFP or DRP mode.648096µA
ICC_MED_PMedium (1.5 A) mode pullup current source when operating in DFP or DRP mode.166180194µA
ICC_HIGH_PHigh (3 A) mode pullup current source when operating in DFP or DRP mode.(1)304330356µA
Control Pins: EN_N, ADDR, INT/OUT3, DIR, ID
VILLow-level control signal input voltage, (EN_N, ADDR)0.4V
VIMMid-level control signal input voltage (ADDR)0.28 × VDD0.56 × VDDV
VIHHigh-level control signal input voltage (EN_N, ADDR)VDD – 0.3VDDV
IIHHigh-level input current–2020µA
IILLow-level input current–1010µA
IID_LEAKAGECurrent leakage on ID pin.VDD = 0 V; ID = 5 V10µA
REN_NInternal pull-up resistance for EN_N.1.1MΩ
RpuInternal pullup resistance (ADDR)588kΩ
RpdInternal pulldown resistance (ADDR)1.1MΩ
VOLLow-level signal output voltage (open-drain) (INT_N/OUT3, ID)IOL = –1.6 mA0.4V
Rp_ODextExternal pullup resistor on open drain IOs (INT_N/OUT3, ID)200kΩ
Rp_TLextTri-level input external pullup resistor (ADDR)4.7kΩ
I2C - SDA/OUT1, SCL/OUT2 can operate from 1.8 or 3.3 V (±10%) when ADDR pin is low or high. (2)
VDD_I2CSupply range for I2C (SDA/OUT1, SCL/OUT2)1.651.83.6V
VIHHigh-level signal voltage1.05V
VILLow-level signal voltage0.4V
VOLLow-level signal output voltage (open drain)IOL = –1.6 mA0.4V
VBUS_DET IO Pins (Connected to System VBUS signal)
VBUS_THRVBUS threshold range2.953.33.8V
RVBUSExternal resistor between VBUS and VBUS_DET pin855887920KΩ
RVBUS_PDInternal pulldown resistance for VBUS_DET95KΩ
DIR pin (Open Drain IO)
VOLLow-level signal output voltageIOL = –1.6 mA0.4V
VCONN
RONOn resistance of the VCONN power FET1.25Ω
VTOLVoltage tolerance on VCONN power FET5.5V
VPASSVoltage to pass through VCONN power FET5.5V
IVCONNVCONN current limit; VCONN is disconnected above the value225300375mA
CBULKBulk capacitance on VCONN; placed on VDD supply10200uF
(1) VDD must be 3.5 V or greater to advertise 3 A current.
(2) When using 3.3 V for I2C, customer must ensure VDD is above 3.0 V at all times.