SLLSFT3A November   2025  – September 2026 MC121-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Timing Requirements
    7. 5.7 Timing Diagrams
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Motor Control
        1. 6.3.1.1 Duty Input
        2. 6.3.1.2 Duty Curve
        3. 6.3.1.3 Motor Start, Speed Change, and Stop
        4. 6.3.1.4 Open-Loop (Duty Cycle) Control
        5. 6.3.1.5 Closed-Loop (Speed) Control
        6. 6.3.1.6 Commutation
          1. 6.3.1.6.1 Hall Sensor
            1. 6.3.1.6.1.1 Field Direction Definition
            2. 6.3.1.6.1.2 Internal Hall Latch Sensor Output
          2. 6.3.1.6.2 Hall Offset
          3. 6.3.1.6.3 Square Commutation
          4. 6.3.1.6.4 Soft Commutation
        7. 6.3.1.7 PWM Modulation Modes
      2. 6.3.2 Protections
        1. 6.3.2.1 Locked Rotor Protection
        2. 6.3.2.2 Current Limit
        3. 6.3.2.3 Overcurrent Protection (OCP)
        4. 6.3.2.4 VM Undervoltage Lockout (UVLO)
        5. 6.3.2.5 VM Over Voltage Protection (OVP)
        6. 6.3.2.6 Thermal Shutdown (TSD)
        7. 6.3.2.7 Integrated Supply (VM) Clamp
    4. 6.4 Device Functional Modes
      1. 6.4.1 Active Mode
      2. 6.4.2 Sleep and Standby Mode
      3. 6.4.3 Fault Mode
      4. 6.4.4 Test Mode and One-Time Programmable Memory
    5. 6.5 Programming
      1. 6.5.1 I2C Communication
        1. 6.5.1.1 I2C Read
        2. 6.5.1.2 I2C Write
  8. 7 Register Map
    1. 7.1 USR_OTP Registers
    2. 7.2 USR_TM Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 External Components
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Bulk Capacitance
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
    5. 8.5 Hall Element Position
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.3.2 Protections

MC121-Q1 integrates protections for rotor lock, current limiting, overcurrent, VM undervoltage, VM overvoltage, and overtemperature events. Table 6-3 indicates the condition for fault mode entry and recovery to active mode.

Table 6-3 Device Fault Action and Response
FAULT CONDITION H-BRIDGE DEVICE LOGIC FG/RD pin fault Indication? RECOVERY
Locked rotor protection Hall transition not detected for tLRD and LRD_RETRY_DIS = 0x0 All FETs disabled

(Hi-Z)

 Enabled Yes Auto retry after tlock_long_retry or tlock_quick_retry
Hall transition not detected for tLRD for 5 consecutive start attempts and LRD_RETRY_DIS = 0x1 All FETs disabled

(Hi-Z)

 Latched; latched faults are cleared only by power reset or sleep wake-up
Current limit IOUTx(Low side) > ILIMIT HS FETs disabled and current recirculation through low side FETs based on PWM_MODE No IOUTx(Low side) < ILIMIT at the start of next output PWM duty cycle
Overvoltage protection VVM > VOVP rising and OVP_EN=0x1 All FETs disabled

(Hi-Z)

 Yes, if FGRD_FAULT_SEL = 0x1

No, if FGRD_FAULT_SEL = 0x0

 VVM < VOVP falling threshold
Overcurrent protection IOUTx > IOCP and OCP_MODE = 0x0 All FETs disabled

(Hi-Z)

 Auto retry after tlock_long_retry
IOUTx > IOCP and OCP_RETRY_MODE = 0x1 Latched after 4 consecutive OCP events; latched faults are cleared only by power reset or sleep wake-up
Thermal Shutdown TJ > TTSD All FETs disabled

(Hi-Z)

 TJ < TTSD - THYS
Undervoltage protection VVM < VUVLO falling All FETs disabled

(Hi-Z)

 Disabled VVM > VUVLO rising threshold
Integrated supply clamp VVM > VCLAMP and VM_CLAMP_DIS = 0x0 HS FETs disabled

(Hi-Z)

 Enabled No VVM < VCLAMP

The FG/RD pin supports feedback to the fan controller for motor speed, rotor lock, or fault detection. Setting the FGRD_MODE bit to 0x0 configures the FG/RD pin for the frequency generator (FG) output. The transitions of the internal hall sensor signal determine the frequency of the FG signal. By setting the FG_MULTIPLIER bits, the FG pin toggles with a factor of 1/2, 1, 2/3, or 2 times the internal hall sensor frequency. The FG_MULTIPLIER bits help minimize system design and firmware changes when swapping motors with different number of magnetic pole pairs or phases. When FG_HALL_RAW_EN is set to 0x0, the FG pin signal corresponds to the hall offset signal used for frequency generator (FG) output. When FG_HALL_RAW_EN = 0x1, the FG pin signal corresponds to the hall latch sensor signal output. The MC121-Q1 does not apply FG_MULTIPLIER setting when FG_HALL_RAW_EN = 0x1.

The FG/RD pin indicates locked rotor condition, device faults, and active mode status according to Table 6-4. The state of the FG pin when motor is in stationary/idle (stopped by DIN = 0% or DOUT_TARGET = 0%) is always complementary to the state used to indicate a locked rotor or device fault condition. For example, if a combination of FGRD_MODE, FGRD_INVERT and FGRD_FAULT_SEL bits indicate locked rotor as an active low signal on FG pin, the state of the FG pin is high (through external pull-up) when the motor is in stationary/idle state.

Fault conditions are reported in the TEST_FAULT and TEST_FAULT_STATUS registers. The TEST_FAULT register provides the real-time status of active faults, while the TEST_FAULT_STATUS register contains fault indicators that persist until cleared by the host.

Table 6-4 FG/RD Pin Behavior
FGRD_MODE bit FGRD_INVERT bit FGRD_FAULT_SEL bit Active Mode Indication Locked rotor fault indication OVP, OCP, TSD, UVLO fault indication
0x0 0x0 0x0 Toggling after 4 hall transitions Asserted low N/A
0x0 0x1 Asserted low
0x1 0x0 Inverted toggling after 4 hall transitions Pulled high N/A
0x1 0x1 Pulled high
0x1 0x0 0x0 Pulled high Asserted low N/A
0x1 Asserted low
0x1 0x0 Asserted low Pulled high N/A
0x1 Pulled high