SLLSFX9A December   2024  – May 2025 MCF8316D

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Output Stage
      2. 7.3.2  Device Interface
        1. 7.3.2.1 Interface - Control and Monitoring
        2. 7.3.2.2 I2C Interface
      3. 7.3.3  Step-Down Mixed-Mode Buck Regulator
        1. 7.3.3.1 Buck in Inductor Mode
        2. 7.3.3.2 Buck in Resistor mode
        3. 7.3.3.3 Buck Regulator with External LDO
        4. 7.3.3.4 AVDD Power Sequencing from Buck Regulator
        5. 7.3.3.5 Mixed Mode Buck Operation and Control
      4. 7.3.4  AVDD Linear Voltage Regulator
      5. 7.3.5  Charge Pump
      6. 7.3.6  Slew Rate Control
      7. 7.3.7  Cross Conduction (Dead Time)
      8. 7.3.8  Motor Control Input Sources
        1. 7.3.8.1 Analog-Mode Motor Control
        2. 7.3.8.2 PWM-Mode Motor Control
        3. 7.3.8.3 I2C-based Motor Control
        4. 7.3.8.4 Frequency-Mode Motor Control
        5. 7.3.8.5 Input Reference Profiles
          1. 7.3.8.5.1 Linear Control Profiles
          2. 7.3.8.5.2 Staircase Control Profiles
          3. 7.3.8.5.3 Forward-Reverse Profiles
          4. 7.3.8.5.4 Multi-Reference Mode Operation
          5. 7.3.8.5.5 Input Reference Transfer Function without Profiler
      9. 7.3.9  Starting the Motor Under Different Initial Conditions
        1. 7.3.9.1 Case 1 – Motor is Stationary
        2. 7.3.9.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 7.3.9.3 Case 3 – Motor is Spinning in the Reverse Direction
      10. 7.3.10 Motor Start Sequence (MSS)
        1. 7.3.10.1 Initial Speed Detect (ISD)
        2. 7.3.10.2 Motor Resynchronization
        3. 7.3.10.3 Reverse Drive
          1. 7.3.10.3.1 Reverse Drive Tuning
        4. 7.3.10.4 Motor Start-up
          1. 7.3.10.4.1 Align
          2. 7.3.10.4.2 Double Align
          3. 7.3.10.4.3 Initial Position Detection (IPD)
            1. 7.3.10.4.3.1 IPD Operation
            2. 7.3.10.4.3.2 IPD Release Mode
            3. 7.3.10.4.3.3 IPD Advance Angle
          4. 7.3.10.4.4 Slow First Cycle Startup
          5. 7.3.10.4.5 Open Loop
          6. 7.3.10.4.6 Transition from Open to Closed Loop
      11. 7.3.11 Closed Loop Operation
        1. 7.3.11.1 Closed Loop Acceleration/Deceleration Slew Rate
        2. 7.3.11.2 Speed PI Control
        3. 7.3.11.3 Current PI Control
        4. 7.3.11.4 Power Control Mode
        5. 7.3.11.5 Current (Torque) Control Mode
        6. 7.3.11.6 Modulation Index Control
        7. 7.3.11.7 Overmodulation
        8. 7.3.11.8 Motor Speed Limit
        9. 7.3.11.9 Input DC Power Limit
      12. 7.3.12 Flux Weakening Control
      13. 7.3.13 Motor Parameters
        1. 7.3.13.1 Motor Resistance
        2. 7.3.13.2 Motor Inductance
        3. 7.3.13.3 Motor Back-EMF constant
      14. 7.3.14 Motor Parameter Extraction Tool (MPET)
      15. 7.3.15 Anti-Voltage Surge (AVS)
      16. 7.3.16 Active Braking
      17. 7.3.17 Output PWM Switching Frequency
      18. 7.3.18 PWM Dithering
      19. 7.3.19 PWM Modulation Schemes
      20. 7.3.20 Dead Time Compensation
      21. 7.3.21 Motor Stop Options
        1. 7.3.21.1 Coast (Hi-Z) Mode
        2. 7.3.21.2 Recirculation Mode
        3. 7.3.21.3 Low-Side Braking
        4. 7.3.21.4 High-Side Braking
        5. 7.3.21.5 Active Spin-Down
      22. 7.3.22 Align Braking
      23. 7.3.23 FG Configuration
        1. 7.3.23.1 FG Output Frequency
        2. 7.3.23.2 FG during Open and Closed Loop States
        3. 7.3.23.3 FG during Fault and Idle States
      24. 7.3.24 Protections
        1. 7.3.24.1  VM Supply Undervoltage Lockout
        2. 7.3.24.2  AVDD Undervoltage Lockout (AVDD_UV)
        3. 7.3.24.3  BUCK Under Voltage Lockout (BUCK_UV)
        4. 7.3.24.4  VCP Charge Pump Undervoltage Lockout (CPUV)
        5. 7.3.24.5  Overvoltage Protection (OVP)
        6. 7.3.24.6  Overcurrent Protection (OCP)
          1. 7.3.24.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
          2. 7.3.24.6.2 OCP Automatic Retry (OCP_MODE = 01b)
        7. 7.3.24.7  Buck Overcurrent Protection
        8. 7.3.24.8  Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)
          1. 7.3.24.8.1 HW_LOCK_ILIMIT Latched Shutdown
          2. 7.3.24.8.2 HW_LOCK_ILIMIT Automatic Recovery
          3. 7.3.24.8.3 HW_LOCK_ILIMIT Report Only
          4. 7.3.24.8.4 HW_LOCK_ILIMIT Disabled
        9. 7.3.24.9  Lock Detection Current Limit (LOCK_ILIMIT)
          1. 7.3.24.9.1 LOCK_ILIMIT Latched Shutdown
          2. 7.3.24.9.2 LOCK_ILIMIT Automatic Recovery
          3. 7.3.24.9.3 LOCK_ILIMIT Report Only
          4. 7.3.24.9.4 LOCK_ILIMIT Disabled
        10. 7.3.24.10 Motor Lock Detection
          1. 7.3.24.10.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 7.3.24.10.2 Lock 2: Abnormal BEMF (ABN_BEMF)
          3. 7.3.24.10.3 Lock3: No-Motor Fault (NO_MTR)
        11. 7.3.24.11 Motor Lock (MTR_LCK)
          1. 7.3.24.11.1 MTR_LCK Latched Shutdown
          2. 7.3.24.11.2 MTR_LCK Automatic Recovery
          3. 7.3.24.11.3 MTR_LCK Report Only
          4. 7.3.24.11.4 MTR_LCK Disabled
        12. 7.3.24.12 EEPROM Fault
        13. 7.3.24.13 I2C CRC Fault
        14. 7.3.24.14 Minimum VM (Undervoltage) Protection
        15. 7.3.24.15 Maximum VM (Overvoltage) Protection
        16. 7.3.24.16 MPET Faults
        17. 7.3.24.17 IPD Faults
        18. 7.3.24.18 FET Thermal Warning (OTW)
        19. 7.3.24.19 FET Thermal Shutdown (TSD_FET)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Standby Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT)
    5. 7.5 External Interface
      1. 7.5.1 DRVOFF Functionality
      2. 7.5.2 DAC outputs
      3. 7.5.3 Current Sense Output
      4. 7.5.4 Oscillator Source
        1. 7.5.4.1 External Clock Source
      5. 7.5.5 External Watchdog
    6. 7.6 EEPROM access and I2C interface
      1. 7.6.1 EEPROM Access
        1. 7.6.1.1 EEPROM Write
        2. 7.6.1.2 EEPROM Read
        3. 7.6.1.3 EEPROM Security
      2. 7.6.2 I2C Serial Interface
        1. 7.6.2.1 I2C Data Word
        2. 7.6.2.2 I2C Write Transaction
        3. 7.6.2.3 I2C Read Transaction
        4. 7.6.2.4 I2C Communication Protocol Packet Examples
        5. 7.6.2.5 I2C Clock Stretching
        6. 7.6.2.6 CRC Byte Calculation
  9. 8 EEPROM (Non-Volatile) Register Map
    1. 8.1 Algorithm_Configuration Registers
    2. 8.2 Fault_Configuration Registers
    3. 8.3 Hardware_Configuration Registers
    4. 8.4 Internal_Algorithm_Configuration Registers
  10. 9 RAM (Volatile) Register Map
    1. 9.1 Fault_Status Registers
    2. 9.2 System_Status Registers
    3. 9.3 Device_Control Registers
    4. 9.4 Algorithm_Control Registers
    5. 9.5 Algorithm_Variables Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Application Curves
        1. 10.2.1.1 Motor startup
        2. 10.2.1.2 MPET
        3. 10.2.1.3 Dead time compensation
        4. 10.2.1.4 Auto handoff
        5. 10.2.1.5 Anti voltage surge (AVS)
        6. 10.2.1.6 Real time variable tracking using DACOUT
    3. 10.3 UL Recognized Component: MCF8316DULVRGFR
      1. 10.3.1 IEC 60730 Functional Safety System
      2. 10.3.2 IEC 60730 Self Test Library (available only in MCF8316DULVRGFR)
    4. 10.4 Power Supply Recommendations
      1. 10.4.1 Bulk Capacitance
    5. 10.5 Layout
      1. 10.5.1 Layout Guidelines
      2. 10.5.2 Layout Example
      3. 10.5.3 Thermal Considerations
        1. 10.5.3.1 Power Dissipation
  12. 11Device and Documentation Support
    1. 11.1 Support Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

8.1 Algorithm_Configuration Registers

Table 8-1 lists the memory-mapped registers for the Algorithm_Configuration registers. All register offset addresses not listed in Table 8-1 are considered as reserved locations and the register contents are not to be modified.

Table 8-1 ALGORITHM_CONFIGURATION Registers
OffsetAcronymRegister NameSection
80hISD_CONFIGISD ConfigurationSection 8.1.1
82hREV_DRIVE_CONFIGReverse Drive ConfigurationSection 8.1.2
84hMOTOR_STARTUP1Motor Startup Configuration1Section 8.1.3
86hMOTOR_STARTUP2Motor Startup Configuration2Section 8.1.4
88hCLOSED_LOOP1Close Loop Configuration1Section 8.1.5
8AhCLOSED_LOOP2Close Loop Configuration2Section 8.1.6
8ChCLOSED_LOOP3Close Loop Configuration3Section 8.1.7
8EhCLOSED_LOOP4Close Loop Configuration4Section 8.1.8
94hREF_PROFILES1Reference Profile Configuration1Section 8.1.9
96hREF_PROFILES2Reference Profile Configuration2Section 8.1.10
98hREF_PROFILES3Reference Profile Configuration3Section 8.1.11
9AhREF_PROFILES4Reference Profile Configuration4Section 8.1.12
9ChREF_PROFILES5Reference Profile Configuration5Section 8.1.13
9EhREF_PROFILES6Reference Profile Configuration6Section 8.1.14

Complex bit access types are encoded to fit into small table cells. Table 8-2 shows the codes that are used for access types in this section.

Table 8-2 Algorithm_Configuration Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

8.1.1 ISD_CONFIG Register (Offset = 80h) [Reset = 00000000h]

ISD_CONFIG is shown in Figure 8-1 and described in Table 8-3.

Return to the Summary Table.

Register to configure initial speed detect settings

Figure 8-1 ISD_CONFIG Register
3130292827262524
PARITYISD_ENBRAKE_ENHIZ_ENRVS_DR_ENRESYNC_ENFW_DRV_RESYN_THR
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
FW_DRV_RESYN_THRBRK_MODEBRK_CONFIGBRK_CURR_THRBRK_TIME
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
BRK_TIMEHIZ_TIMESTAT_DETECT_THR
R/W-0hR/W-0hR/W-0h
76543210
STAT_DETECT_THRREV_DRV_HANDOFF_THRREV_DRV_OPEN_LOOP_CURRENT
R/W-0hR/W-0hR/W-0h
Table 8-3 ISD_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR0h Parity bit
30ISD_ENR/W0h ISD enable
  • 0h = Disable
  • 1h = Enable
29BRAKE_ENR/W0h ISD brake enable
  • 0h = Disable
  • 1h = Enable
28HIZ_ENR/W0h ISD Hi-Z enable
  • 0h = Disable
  • 1h = Enable
27RVS_DR_ENR/W0h Reverse drive enable
  • 0h = Disable
  • 1h = Enable
26RESYNC_ENR/W0h Resynchronization enable
  • 0h = Disable
  • 1h = Enable
25-22FW_DRV_RESYN_THRR/W0h Minimum speed threshold to resynchronize to close loop (% of MAX_SPEED)
  • 0h = 5%
  • 1h = 10%
  • 2h = 15%
  • 3h = 20%
  • 4h = 25%
  • 5h = 30%
  • 6h = 35%
  • 7h = 40%
  • 8h = 45%
  • 9h = 50%
  • Ah = Not Applicable
  • Bh = Not Applicable
  • Ch = Not Applicable
  • Dh = Not Applicable
  • Eh = Not Applicable
  • Fh = Not Applicable
21BRK_MODER/W0h Brake mode
  • 0h = All three high side FETs turned ON
  • 1h = All three low side FETs turned ON
20BRK_CONFIGR/W0h Brake configuration
  • 0h = Brake time is used to come out of Brake state
  • 1h = Brake current threshold and Brake time is used to come out of Brake state
19-17BRK_CURR_THRR/W0h Brake current threshold
  • 0h = 0.1A
  • 1h = 0.2A
  • 2h = 0.3A
  • 3h = 0.5A
  • 4h = 1.0A
  • 5h = 2.0A
  • 6h = Not Applicable
  • 7h = Not Applicable
16-13BRK_TIMER/W0h Brake time
  • 0h = 10ms
  • 1h = 50ms
  • 2h = 100ms
  • 3h = 200ms
  • 4h = 300ms
  • 5h = 400ms
  • 6h = 500ms
  • 7h = 750ms
  • 8h = 1s
  • 9h = 2s
  • Ah = 3s
  • Bh = 4s
  • Ch = 5s
  • Dh = 7.5s
  • Eh = 10s
  • Fh = 15s
12-9HIZ_TIMER/W0h Hi-Z time
  • 0h = 10ms
  • 1h = 50ms
  • 2h = 100ms
  • 3h = 200ms
  • 4h = 300ms
  • 5h = 400ms
  • 6h = 500ms
  • 7h = 750ms
  • 8h = 1s
  • 9h = 2s
  • Ah = 3s
  • Bh = 4s
  • Ch = 5s
  • Dh = 7.5s
  • Eh = 10s
  • Fh = 15s
8-6STAT_DETECT_THRR/W0h BEMF threshold to detect if motor is stationary
  • 0h = 50mV
  • 1h = 75mV
  • 2h = 100mV
  • 3h = 250mV
  • 4h = 500mV
  • 5h = 750mV
  • 6h = 1000mV
  • 7h = 1500mV
5-2REV_DRV_HANDOFF_THRR/W0h Speed threshold used to transition to open loop during reverse drive (% of MAX_SPEED)
  • 0h = 2.5%
  • 1h = 5%
  • 2h = 7.5%
  • 3h = 10%
  • 4h = 12.5%
  • 5h = 15%
  • 6h = 20%
  • 7h = 25%
  • 8h = 30%
  • 9h = 40%
  • Ah = 50%
  • Bh = Not Applicable
  • Ch = Not Applicable
  • Dh = Not Applicable
  • Eh = Not Applicable
  • Fh = Not Applicable
1-0REV_DRV_OPEN_LOOP_CURRENTR/W0h Open loop current limit during reverse drive
  • 0h = 1.5A
  • 1h = 2.5A
  • 2h = 3.5A
  • 3h = 5.0A

8.1.2 REV_DRIVE_CONFIG Register (Offset = 82h) [Reset = 00000000h]

REV_DRIVE_CONFIG is shown in Figure 8-2 and described in Table 8-4.

Return to the Summary Table.

Register to configure reverse drive settings

Figure 8-2 REV_DRIVE_CONFIG Register
3130292827262524
PARITYREV_DRV_OPEN_LOOP_ACCEL_A1REV_DRV_OPEN_LOOP_ACCEL_A2
R-0hR/W-0hR/W-0h
2322212019181716
REV_DRV_OPEN_LOOP_ACCEL_A2ACTIVE_BRAKE_CURRENT_LIMITACTIVE_BRAKE_KP
R/W-0hR/W-0hR/W-0h
15141312111098
ACTIVE_BRAKE_KPACTIVE_BRAKE_KI
R/W-0hR/W-0h
76543210
ACTIVE_BRAKE_KI
R/W-0h
Table 8-4 REV_DRIVE_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR0h Parity bit
30-27REV_DRV_OPEN_LOOP_ACCEL_A1R/W0h Open loop acceleration coefficient A1 during reverse drive
  • 0h = 0.1Hz/s
  • 1h = 0.5Hz/s
  • 2h = 1Hz/s
  • 3h = 2.5Hz/s
  • 4h = 5Hz/s
  • 5h = 10Hz/s
  • 6h = 25Hz/s
  • 7h = 50Hz/s
  • 8h = 75Hz/s
  • 9h = 100Hz/s
  • Ah = 250Hz/s
  • Bh = 500Hz/s
  • Ch = 750Hz/s
  • Dh = 1000Hz/s
  • Eh = 5000Hz/s
  • Fh = 10000Hz/s
26-23REV_DRV_OPEN_LOOP_ACCEL_A2R/W0h Open loop acceleration coefficient A2 during reverse drive
  • 0h = 0.0Hz/s2
  • 1h = 0.5Hz/s2
  • 2h = 1Hz/s2
  • 3h = 2.5Hz/s2
  • 4h = 5Hz/s2
  • 5h = 10Hz/s2
  • 6h = 25Hz/s2
  • 7h = 50Hz/s2
  • 8h = 75Hz/s2
  • 9h = 100Hz/s2
  • Ah = 250Hz/s2
  • Bh = 500Hz/s2
  • Ch = 750Hz/s2
  • Dh = 1000Hz/s2
  • Eh = 5000Hz/s2
  • Fh = 10000Hz/s2
22-20ACTIVE_BRAKE_CURRENT_LIMITR/W0h Bus current limit during active braking
  • 0h = 0.5A
  • 1h = 1.0A
  • 2h = 2.0A
  • 3h = 3.0A
  • 4h = 4.0A
  • 5h = 5.0A
  • 6h = 6.0A
  • 7h = 7.0A
19-10ACTIVE_BRAKE_KPR/W0h 10-bit value for active braking loop Kp. Kp = ACTIVE_BRAKE_KP / 27
9-0ACTIVE_BRAKE_KIR/W0h 10-bit value for active braking loop Ki. Ki = ACTIVE_BRAKE_KI / 29

8.1.3 MOTOR_STARTUP1 Register (Offset = 84h) [Reset = 00000000h]

MOTOR_STARTUP1 is shown in Figure 8-3 and described in Table 8-5.

Return to the Summary Table.

Register to configure motor startup settings1

Figure 8-3 MOTOR_STARTUP1 Register
3130292827262524
PARITYMTR_STARTUPALIGN_SLOW_RAMP_RATEALIGN_TIME
R-0hR/W-0hR/W-0hR/W-0h
2322212019181716
ALIGN_TIMEALIGN_OR_SLOW_CURRENT_ILIMITIPD_CLK_FREQ
R/W-0hR/W-0hR/W-0h
15141312111098
IPD_CLK_FREQIPD_CURR_THRIPD_RLS_MODE
R/W-0hR/W-0hR/W-0h
76543210
IPD_ADV_ANGLEIPD_REPEATRESERVEDIQ_RAMP_ENACTIVE_BRAKE_ENREV_DRV_CONFIG
R/W-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0h
Table 8-5 MOTOR_STARTUP1 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR0h Parity bit
30-29MTR_STARTUPR/W0h Motor start-up method
  • 0h = Align
  • 1h = Double Align
  • 2h = IPD
  • 3h = Slow first cycle
28-25ALIGN_SLOW_RAMP_RATER/W0h Align, slow first cycle and open loop current ramp rate
  • 0h = 0.1A/s
  • 1h = 1A/s
  • 2h = 5A/s
  • 3h = 10A/s
  • 4h = 15A/s
  • 5h = 25A/s
  • 6h = 50A/s
  • 7h = 100A/s
  • 8h = 150A/s
  • 9h = 200A/s
  • Ah = 250A/s
  • Bh = 500A/s
  • Ch = 1000A/s
  • Dh = 2000A/s
  • Eh = 5000A/s
  • Fh = No Limit A/s
24-21ALIGN_TIMER/W0h Align time
  • 0h = 10ms
  • 1h = 50ms
  • 2h = 100ms
  • 3h = 200ms
  • 4h = 300ms
  • 5h = 400ms
  • 6h = 500ms
  • 7h = 750ms
  • 8h = 1s
  • 9h = 1.5s
  • Ah = 2s
  • Bh = 3s
  • Ch = 4s
  • Dh = 5s
  • Eh = 7.5s
  • Fh = 10s
20-17ALIGN_OR_SLOW_CURRENT_ILIMITR/W0h Align or slow first cycle current limit
  • 0h = 0.125A
  • 1h = 0.25A
  • 2h = 0.5A
  • 3h = 1.0A
  • 4h = 1.5A
  • 5h = 2.0A
  • 6h = 2.5A
  • 7h = 3.0A
  • 8h = 3.5A
  • 9h = 4.0A
  • Ah = 4.5A
  • Bh = 5.0A
  • Ch = 5.5A
  • Dh = 6.0A
  • Eh = 7.0A
  • Fh = 8.0A
16-14IPD_CLK_FREQR/W0h IPD clock frequency
  • 0h = 50Hz
  • 1h = 100Hz
  • 2h = 250Hz
  • 3h = 500Hz
  • 4h = 1000Hz
  • 5h = 2000Hz
  • 6h = 5000Hz
  • 7h = 10000Hz
13-9IPD_CURR_THRR/W0h IPD current threshold
  • 0h = 0.25A
  • 1h = 0.5A
  • 2h = 0.75A
  • 3h = 1.0A
  • 4h = 1.25A
  • 5h = 1.5A
  • 6h = 2.0A
  • 7h = 2.5A
  • 8h = 3.0A
  • 9h = 3.667A
  • Ah = 4.0A
  • Bh = 4.667A
  • Ch = 5.0A
  • Dh = 5.333A
  • Eh = 6.0A
  • Fh = 6.667A
  • 10h = 7.333A
  • 11h = 8.0A
  • 12h = Not Applicable
  • 13h = Not Applicable
  • 14h = Not Applicable
  • 15h = Not Applicable
  • 16h = Not Applicable
  • 17h = Not Applicable
  • 18h = Not Applicable
  • 19h = Not Applicable
  • 1Ah = Not Applicable
  • 1Bh = Not Applicable
  • 1Ch = Not Applicable
  • 1Dh = Not Applicable
  • 1Eh = Not Applicable
  • 1Fh = Not Applicable
8IPD_RLS_MODER/W0h IPD release mode
  • 0h = Brake
  • 1h = Tristate
7-6IPD_ADV_ANGLER/W0h IPD advance angle
  • 0h = 0°
  • 1h = 30°
  • 2h = 60°
  • 3h = 90°
5-4IPD_REPEATR/W0h Number of times IPD is executed
  • 0h = 1 time
  • 1h = 2 times
  • 2h = 3 times
  • 3h = 4 times
3RESERVEDR0h Reserved
2IQ_RAMP_ENR/W0h Iq reference ramp down during transition from open loop to closed loop
  • 0h = Disable Iq ramp down
  • 1h = Enable Iq ramp down
1ACTIVE_BRAKE_ENR/W0h Enable active braking
  • 0h = Disable Active Brake
  • 1h = Enable Active Brake
0REV_DRV_CONFIGR/W0h Choose between forward and reverse drive setting for reverse drive
  • 0h = Open loop current, A1, A2 based on forward drive
  • 1h = Open loop current, A1, A2 based on reverse drive

8.1.4 MOTOR_STARTUP2 Register (Offset = 86h) [Reset = 00000000h]

MOTOR_STARTUP2 is shown in Figure 8-4 and described in Table 8-6.

Return to the Summary Table.

Register to configure motor startup settings2

Figure 8-4 MOTOR_STARTUP2 Register
3130292827262524
PARITYOL_ILIMITOL_ACC_A1
R-0hR/W-0hR/W-0h
2322212019181716
OL_ACC_A1OL_ACC_A2AUTO_HANDOFF_ENOPN_CL_HANDOFF_THR
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
OPN_CL_HANDOFF_THRALIGN_ANGLE
R/W-0hR/W-0h
76543210
SLOW_FIRST_CYC_FREQFIRST_CYCLE_FREQ_SELTHETA_ERROR_RAMP_RATE
R/W-0hR/W-0hR/W-0h
Table 8-6 MOTOR_STARTUP2 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR0h Parity bit
30-27OL_ILIMITR/W0h Open loop current limit
  • 0h = 0.125A
  • 1h = 0.25A
  • 2h = 0.5A
  • 3h = 1.0A
  • 4h = 1.5A
  • 5h = 2.0A
  • 6h = 2.5A
  • 7h = 3.0A
  • 8h = 3.5A
  • 9h = 4.0A
  • Ah = 4.5A
  • Bh = 5.0A
  • Ch = 5.5A
  • Dh = 6.0A
  • Eh = 7.0A
  • Fh = 8.0A
26-23OL_ACC_A1R/W0h Open loop acceleration coefficient A1
  • 0h = 0.1Hz/s
  • 1h = 0.5Hz/s
  • 2h = 1Hz/s
  • 3h = 2.5Hz/s
  • 4h = 5Hz/s
  • 5h = 10Hz/s
  • 6h = 25Hz/s
  • 7h = 50Hz/s
  • 8h = 75Hz/s
  • 9h = 100Hz/s
  • Ah = 250Hz/s
  • Bh = 500Hz/s
  • Ch = 750Hz/s
  • Dh = 1000Hz/s
  • Eh = 5000Hz/s
  • Fh = 10000Hz/s
22-19OL_ACC_A2R/W0h Open loop acceleration coefficient A2
  • 0h = 0.0Hz/s2
  • 1h = 0.5Hz/s2
  • 2h = 1Hz/s2
  • 3h = 2.5Hz/s2
  • 4h = 5Hz/s2
  • 5h = 10Hz/s2
  • 6h = 25Hz/s2
  • 7h = 50Hz/s2
  • 8h = 75Hz/s2
  • 9h = 100Hz/s2
  • Ah = 250Hz/s2
  • Bh = 500Hz/s2
  • Ch = 750Hz/s2
  • Dh = 1000Hz/s2
  • Eh = 5000Hz/s2
  • Fh = 10000Hz/s2
18AUTO_HANDOFF_ENR/W0h Auto handoff enable
  • 0h = Disable Auto Handoff (and use OPN_CL_HANDOFF_THR)
  • 1h = Enable Auto Handoff
17-13OPN_CL_HANDOFF_THRR/W0h Open to closed loop handoff threshold (% of MAX_SPEED)
  • 0h = 1%
  • 1h = 2%
  • 2h = 3%
  • 3h = 4%
  • 4h = 5%
  • 5h = 6%
  • 6h = 7%
  • 7h = 8%
  • 8h = 9%
  • 9h = 10%
  • Ah = 11%
  • Bh = 12%
  • Ch = 13%
  • Dh = 14%
  • Eh = 15%
  • Fh = 16%
  • 10h = 17%
  • 11h = 18%
  • 12h = 19%
  • 13h = 20%
  • 14h = 22.5%
  • 15h = 25%
  • 16h = 27.5%
  • 17h = 30%
  • 18h = 32.5%
  • 19h = 35%
  • 1Ah = 37.5%
  • 1Bh = 40%
  • 1Ch = 42.5%
  • 1Dh = 45%
  • 1Eh = 47.5%
  • 1Fh = 50%
12-8ALIGN_ANGLER/W0h Align angle
  • 0h = 0°
  • 1h = 10°
  • 2h = 20°
  • 3h = 30°
  • 4h = 45°
  • 5h = 60°
  • 6h = 70°
  • 7h = 80°
  • 8h = 90°
  • 9h = 110°
  • Ah = 120°
  • Bh = 135°
  • Ch = 150°
  • Dh = 160°
  • Eh = 170°
  • Fh = 180°
  • 10h = 190°
  • 11h = 210°
  • 12h = 225°
  • 13h = 240°
  • 14h = 250°
  • 15h = 260°
  • 16h = 270°
  • 17h = 280°
  • 18h = 290°
  • 19h = 315°
  • 1Ah = 330°
  • 1Bh = 340°
  • 1Ch = 350°
  • 1Dh = Not Applicable
  • 1Eh = Not Applicable
  • 1Fh = Not Applicable
7-4SLOW_FIRST_CYC_FREQR/W0h Frequency of first cycle in open loop start-up (% of MAX_SPEED)
  • 0h = 0.1%
  • 1h = 0.3%
  • 2h = 0.5%
  • 3h = 0.7%
  • 4h = 1.0%
  • 5h = 1.5%
  • 6h = 2.0%
  • 7h = 2.5%
  • 8h = 3.0%
  • 9h = 4.0%
  • Ah = 5.0%
  • Bh = 7.5%
  • Ch = 10.0%
  • Dh = 15%
  • Eh = 20%
  • Fh = 25%
3FIRST_CYCLE_FREQ_SELR/W0h First cycle frequency in open loop for align, double align and IPD start-up
  • 0h = 0Hz
  • 1h = Defined by SLOW_FIRST_CYC_FREQ
2-0THETA_ERROR_RAMP_RATER/W0h Ramp rate for reducing difference between estimated theta and open loop theta
  • 0h = 0.01 deg/ms
  • 1h = 0.05 deg/ms
  • 2h = 0.1 deg/ms
  • 3h = 0.15 deg/ms
  • 4h = 0.2 deg/ms
  • 5h = 0.5 deg/ms
  • 6h = 1 deg/ms
  • 7h = 2 deg/ms

8.1.5 CLOSED_LOOP1 Register (Offset = 88h) [Reset = 00000000h]

CLOSED_LOOP1 is shown in Figure 8-5 and described in Table 8-7.

Return to the Summary Table.

Register to configure close loop settings1

Figure 8-5 CLOSED_LOOP1 Register
3130292827262524
PARITYOVERMODULATION_ENABLECL_ACCRESERVED
R-0hR/W-0hR/W-0hR-0h
2322212019181716
CL_DECPWM_FREQ_OUT
R/W-0hR/W-0h
15141312111098
PWM_FREQ_OUTPWM_MODEFG_SELFG_DIV
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
FG_CONFIGFG_BEMF_THRAVS_ENDEADTIME_COMP_ENRESERVEDLOW_SPEED_RECIRC_BRAKE_EN
R/W-0hR/W-0hR/W-0hR/W-0hR-0hR/W-0h
Table 8-7 CLOSED_LOOP1 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR0h Parity bit
30OVERMODULATION_ENABLER/W0h Enable overmodulation
  • 0h = Disable overmodulation
  • 1h = Enable overmodulation
29-25CL_ACCR/W0h Closed loop acceleration (Speed mode: Hz/s Power mode: deciWatts/s Torque mode: centiA/s duty cycle mode: milliUnit/s) deciWatt: 0.1W centiA: 0.01A milliUnit: 0.001%
  • 0h = 0.5
  • 1h = 1
  • 2h = 2.5
  • 3h = 5
  • 4h = 7.5
  • 5h = 10
  • 6h = 20
  • 7h = 40
  • 8h = 60
  • 9h = 80
  • Ah = 100
  • Bh = 200
  • Ch = 300
  • Dh = 400
  • Eh = 500
  • Fh = 600
  • 10h = 700
  • 11h = 800
  • 12h = 900
  • 13h = 1000
  • 14h = 2000
  • 15h = 4000
  • 16h = 6000
  • 17h = 8000
  • 18h = 10000
  • 19h = 20000
  • 1Ah = 30000
  • 1Bh = 40000
  • 1Ch = 50000
  • 1Dh = 60000
  • 1Eh = 70000
  • 1Fh = No limit
24RESERVEDR0h Reserved
23-19CL_DECR/W0h Closed loop deceleration (Speed mode: Hz/s Power mode: deciWatts/s Torque mode: centiA/s duty cycle mode: milliUnit/s) If AVS is enabled in speed or power mode, the current is clamped to 0 only if negative iqRef is set by outer PI (speed/power) loop deciWatt: 0.1W centiA: 0.01A milliUnit: 0.001%
  • 0h = 0.5
  • 1h = 1
  • 2h = 2.5
  • 3h = 5
  • 4h = 7.5
  • 5h = 10
  • 6h = 20
  • 7h = 40
  • 8h = 60
  • 9h = 80
  • Ah = 100
  • Bh = 200
  • Ch = 300
  • Dh = 400
  • Eh = 500
  • Fh = 600
  • 10h = 700
  • 11h = 800
  • 12h = 900
  • 13h = 1000
  • 14h = 2000
  • 15h = 4000
  • 16h = 6000
  • 17h = 8000
  • 18h = 10000
  • 19h = 20000
  • 1Ah = 30000
  • 1Bh = 40000
  • 1Ch = 50000
  • 1Dh = 60000
  • 1Eh = 70000
  • 1Fh = No limit
18-15PWM_FREQ_OUTR/W0h PWM output frequency
  • 0h = 10kHz
  • 1h = 15kHz
  • 2h = 20kHz
  • 3h = 25kHz
  • 4h = 30kHz
  • 5h = 35kHz
  • 6h = 40kHz
  • 7h = 45kHz
  • 8h = 50kHz
  • 9h = 55kHz
  • Ah = 60kHz
  • Bh = Not Applicable
  • Ch = Not Applicable
  • Dh = Not Applicable
  • Eh = Not Applicable
  • Fh = Not Applicable
14PWM_MODER/W0h PWM modulation
  • 0h = Continuous Space Vector Modulation
  • 1h = Discontinuous Space Vector Modulation
13-12FG_SELR/W0h FG select
  • 0h = Output FG in ISD, open loop and closed loop
  • 1h = Output FG in only closed loop
  • 2h = Output FG in open loop for the first try.
  • 3h = Not Applicable
11-8FG_DIVR/W0h FG division factor
  • 0h = 3x electrical speed
  • 1h = Divide by 1 (2-pole motor mechanical speed)
  • 2h = Divide by 2 (4-pole motor mechanical speed)
  • 3h = Divide by 3 (6-pole motor mechanical speed)
  • 4h = Divide by 4 (8-pole motor mechanical speed) ...
  • Fh = Divide by 15 (30-pole motor mechanical speed)
7FG_CONFIGR/W0h FG output configuration. BEMF threshold defined by FG_BEMF_THR
  • 0h = FG active as long as motor is driven
  • 1h = FG active till BEMF drops below BEMF threshold
6-4FG_BEMF_THRR/W0h FG output BEMF threshold
  • 0h = +/- 1mV
  • 1h = +/- 2mV
  • 2h = +/- 5mV
  • 3h = +/- 10mV
  • 4h = +/- 20mV
  • 5h = +/- 30mV
  • 6h = Not Applicable
  • 7h = Not Applicable
3AVS_ENR/W0h AVS enable
  • 0h = Disable
  • 1h = Enable
2DEADTIME_COMP_ENR/W0h Deadtime compensation enable
  • 0h = Disable
  • 1h = Enable
1RESERVEDR0h Reserved
0LOW_SPEED_RECIRC_BRAKE_ENR/W0h Stop mode applied when stop mode is recirculation brake and motor in align or open loop state
  • 0h = Hi-z
  • 1h = Low Side Brake

8.1.6 CLOSED_LOOP2 Register (Offset = 8Ah) [Reset = 00000000h]

CLOSED_LOOP2 is shown in Figure 8-6 and described in Table 8-8.

Return to the Summary Table.

Register to configure close loop settings2

Figure 8-6 CLOSED_LOOP2 Register
3130292827262524
PARITYMTR_STOPMTR_STOP_BRK_TIME
R-0hR/W-0hR/W-0h
2322212019181716
ACT_SPIN_THRBRAKE_SPEED_THRESHOLD
R/W-0hR/W-0h
15141312111098
MOTOR_RES
R/W-0h
76543210
MOTOR_IND
R/W-0h
Table 8-8 CLOSED_LOOP2 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR0h Parity bit
30-28MTR_STOPR/W0h Motor stop mode
  • 0h = Hi-z
  • 1h = Recirculation Stop
  • 2h = Low side braking
  • 3h = High side braking
  • 4h = Active spin down
  • 5h = Not Applicable
  • 6h = Not Applicable
  • 7h = Not Applicable
27-24MTR_STOP_BRK_TIMER/W0h Brake time during motor stop
  • 0h = 1ms
  • 1h = 1ms
  • 2h = 1ms
  • 3h = 1ms
  • 4h = 1ms
  • 5h = 5ms
  • 6h = 10ms
  • 7h = 50ms
  • 8h = 100ms
  • 9h = 250ms
  • Ah = 500ms
  • Bh = 1000ms
  • Ch = 2500ms
  • Dh = 5000ms
  • Eh = 10000ms
  • Fh = 15000ms
23-20ACT_SPIN_THRR/W0h Speed threshold for active spin down (% of MAX_SPEED)
  • 0h = 100 %
  • 1h = 90 %
  • 2h = 80 %
  • 3h = 70 %
  • 4h = 60%
  • 5h = 50 %
  • 6h = 45 %
  • 7h = 40 %
  • 8h = 35 %
  • 9h = 30 %
  • Ah = 25 %
  • Bh = 20 %
  • Ch = 15 %
  • Dh = 10 %
  • Eh = 5 %
  • Fh = 2.5 %
19-16BRAKE_SPEED_THRESHOLDR/W0h Speed threshold for BRAKE pin and Motor stop (Low side Braking or High Side Braking or Align Braking) (% of MAX_SPEED)
  • 0h = 100 %
  • 1h = 90 %
  • 2h = 80 %
  • 3h = 70 %
  • 4h = 60%
  • 5h = 50 %
  • 6h = 45 %
  • 7h = 40 %
  • 8h = 35 %
  • 9h = 30 %
  • Ah = 25 %
  • Bh = 20 %
  • Ch = 15 %
  • Dh = 10 %
  • Eh = 5 %
  • Fh = 2.5 %
15-8MOTOR_RESR/W0h 8-bit values for motor phase resistance. See Table 6-2 for values of phase resistance
7-0MOTOR_INDR/W0h 8-bit values for motor phase inductance. See Table 6-3 for values of phase inductance

8.1.7 CLOSED_LOOP3 Register (Offset = 8Ch) [Reset = 00000000h]

CLOSED_LOOP3 is shown in Figure 8-7 and described in Table 8-9.

Return to the Summary Table.

Register to configure close loop settings3

Figure 8-7 CLOSED_LOOP3 Register
3130292827262524
PARITYMOTOR_BEMF_CONST
R-0hR/W-0h
2322212019181716
MOTOR_BEMF_CONSTCURR_LOOP_KP
R/W-0hR/W-0h
15141312111098
CURR_LOOP_KPCURR_LOOP_KI
R/W-0hR/W-0h
76543210
CURR_LOOP_KISPD_LOOP_KP
R/W-0hR/W-0h
Table 8-9 CLOSED_LOOP3 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR0h Parity bit
30-23MOTOR_BEMF_CONSTR/W0h 8-bit values for motor BEMF Constant. See Table 6-4 for values of BEMF constant
22-13CURR_LOOP_KPR/W0h 10-bit value for current Iq and Id loop Kp. Kp = 8LSB of CURR_LOOP_KP / 10^2MSB of CURR_LOOP_KP. Set to 0 for auto calculation of current Kp and Ki
12-3CURR_LOOP_KIR/W0h 10-bit value for current Iq and Id loop Ki. Ki = 1000 * 8LSB of CURR_LOOP_KI / 10^2MSB of CURR_LOOP_KI. Set to 0 for auto calculation of current Kp and Ki
2-0SPD_LOOP_KPR/W0h 3 MSB bits for speed loop Kp. Kp = 0.01 * 8LSB of SPD_LOOP_KP / 10^2MSB of SPD_LOOP_KP

8.1.8 CLOSED_LOOP4 Register (Offset = 8Eh) [Reset = 00000000h]

CLOSED_LOOP4 is shown in Figure 8-8 and described in Table 8-10.

Return to the Summary Table.

Register to configure close loop settings4

Figure 8-8 CLOSED_LOOP4 Register
3130292827262524
PARITYSPD_LOOP_KP
R-0hR/W-0h
2322212019181716
SPD_LOOP_KI
R/W-0h
15141312111098
SPD_LOOP_KIMAX_SPEED
R/W-0hR/W-0h
76543210
MAX_SPEED
R/W-0h
Table 8-10 CLOSED_LOOP4 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR0h Parity bit
30-24SPD_LOOP_KPR/W0h 7 LSB bits for speed loop Kp. Kp = 0.01 * 8LSB of SPD_LOOP_KP / 10^2MSB of SPD_LOOP_KP
23-14SPD_LOOP_KIR/W0h 10 bit value for speed loop Ki. Ki = 0.1 * 8LSB of SPD_LOOP_KI / 10^2MSB of SPD_LOOP_KI
13-0MAX_SPEEDR/W0h 14-bit value for setting maximum motor speed in electrical Hz. Maximum motor electrical speed (Hz): {MAX_SPEED/6} For example: if MAX_SPEED is 0x2710, then maximum motor speed (Hz) = 10000(0x2710)/6 = 1666Hz

8.1.9 REF_PROFILES1 Register (Offset = 94h) [Reset = 00000000h]

REF_PROFILES1 is shown in Figure 8-9 and described in Table 8-11.

Return to the Summary Table.

Register to configure Reference profile1

Figure 8-9 REF_PROFILES1 Register
3130292827262524
PARITYREF_PROFILE_CONFIGDUTY_ON1
R-0hR/W-0hR/W-0h
2322212019181716
DUTY_ON1DUTY_OFF1
R/W-0hR/W-0h
15141312111098
DUTY_OFF1DUTY_CLAMP1
R/W-0hR/W-0h
76543210
DUTY_CLAMP1DUTY_A
R/W-0hR/W-0h
Table 8-11 REF_PROFILES1 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR0h Parity bit
30-29REF_PROFILE_CONFIGR/W0h Configuration for reference profiles
  • 0h = Reference/Equation
  • 1h = Linear Profile
  • 2h = Staircase Profile
  • 3h = Forward-Reverse Profile
28-21DUTY_ON1R/W0h Turn-on duty cycle (%) = {(DUTY_ON1/256)*100}
20-13DUTY_OFF1R/W0h Turn-off duty cycle (%) = {(DUTY_OFF1/256)*100}
12-5DUTY_CLAMP1R/W0h Duty cycle for clamping speed (%) = {(DUTY_CLAMP1/256)*100}
4-0DUTY_AR/W0h 5 MSB bits for duty cycle A

8.1.10 REF_PROFILES2 Register (Offset = 96h) [Reset = 00000000h]

REF_PROFILES2 is shown in Figure 8-10 and described in Table 8-12.

Return to the Summary Table.

Register to configure Reference profile2

Figure 8-10 REF_PROFILES2 Register
3130292827262524
PARITYDUTY_ADUTY_B
R-0hR/W-0hR/W-0h
2322212019181716
DUTY_BDUTY_C
R/W-0hR/W-0h
15141312111098
DUTY_CDUTY_D
R/W-0hR/W-0h
76543210
DUTY_DDUTY_E
R/W-0hR/W-0h
Table 8-12 REF_PROFILES2 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR0h Parity bit
30-28DUTY_AR/W0h 3 LSB bits for duty cycle A Duty cycle A (%) = {(DUTY_A/256)*100}
27-20DUTY_BR/W0h Duty cycle B (%) = {(DUTY_B/256)*100}
19-12DUTY_CR/W0h Duty cycle C (%) = {(DUTY_C/256)*100}
11-4DUTY_DR/W0h Duty cycle D (%) = {(DUTY_D/256)*100}
3-0DUTY_ER/W0h 4 MSB bits for Duty cycle E

8.1.11 REF_PROFILES3 Register (Offset = 98h) [Reset = 00000000h]

REF_PROFILES3 is shown in Figure 8-11 and described in Table 8-13.

Return to the Summary Table.

Register to configure Reference profile3

Figure 8-11 REF_PROFILES3 Register
3130292827262524
PARITYDUTY_EDUTY_ON2
R-0hR/W-0hR/W-0h
2322212019181716
DUTY_ON2DUTY_OFF2
R/W-0hR/W-0h
15141312111098
DUTY_OFF2DUTY_CLAMP2
R/W-0hR/W-0h
76543210
DUTY_CLAMP2DUTY_HYSRESERVED
R/W-0hR/W-0hR-0h
Table 8-13 REF_PROFILES3 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR0h Parity bit
30-27DUTY_ER/W0h 4 LSB bits for Duty cycle E Duty cycle E (%) = {(DUTY_E/256)*100}
26-19DUTY_ON2R/W0h Turn-on duty cycle (%) = {(DUTY_ON2/256)*100}
18-11DUTY_OFF2R/W0h Turn-off duty cycle (%) = {(DUTY_OFF2/256)*100}
10-3DUTY_CLAMP2R/W0h Duty cycle for clamping speed (%) = {(DUTY_CLAMP1/256)*100}
2-1DUTY_HYSR/W0h Duty hysteresis for speed reference mode
  • 0h = 0%
  • 1h = 1%
  • 2h = 2%
  • 3h = 3%
0RESERVEDR0h Reserved

8.1.12 REF_PROFILES4 Register (Offset = 9Ah) [Reset = 00000000h]

REF_PROFILES4 is shown in Figure 8-12 and described in Table 8-14.

Return to the Summary Table.

Register to configure Reference profile4

Figure 8-12 REF_PROFILES4 Register
3130292827262524
PARITYREF_OFF1
R-0hR/W-0h
2322212019181716
REF_OFF1REF_CLAMP1
R/W-0hR/W-0h
15141312111098
REF_CLAMP1REF_A
R/W-0hR/W-0h
76543210
REF_AREF_B
R/W-0hR/W-0h
Table 8-14 REF_PROFILES4 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR0h Parity bit
30-23REF_OFF1R/W0h Turn off reference (% of Maximum Reference) = {(REF_OFF1/256)*100}
22-15REF_CLAMP1R/W0h Clamp Ref 1 (% of Maximum Reference) = {(REF_CLAMP1/256)*100}
14-7REF_AR/W0h Ref A (% of Maximum Reference) = {(REF_A/256)*100}
6-0REF_BR/W0h 7 MSB of REF_B configuration

8.1.13 REF_PROFILES5 Register (Offset = 9Ch) [Reset = 00000000h]

REF_PROFILES5 is shown in Figure 8-13 and described in Table 8-15.

Return to the Summary Table.

Register to configure Reference profile5

Figure 8-13 REF_PROFILES5 Register
3130292827262524
PARITYREF_BREF_C
R-0hR/W-0hR/W-0h
2322212019181716
REF_CREF_D
R/W-0hR/W-0h
15141312111098
REF_DREF_E
R/W-0hR/W-0h
76543210
REF_EMIN_DUTYVOLTAGE_MODE_CONFIGDUTY_COMMAND_FILTERRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR-0h
Table 8-15 REF_PROFILES5 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR0h Parity bit
30REF_BR/W0h 1 LSB of REF_B configuration. Ref B(% of Maximum Reference) = {(REF_B/256)*100}
29-22REF_CR/W0h Ref C (% of Maximum Reference) = {(REF_C/256)*100}
21-14REF_DR/W0h Ref D (% of Maximum Reference) = {(REF_D/256)*100}
13-6REF_ER/W0h Ref E(% of Maximum Reference) = {(REF_E/256)*100}
5-4MIN_DUTYR/W0h Minimum input duty to start driving the motor
  • 0h = 1 %
  • 1h = 3 %
  • 2h = 5 %
  • 3h = 10 %
3-2VOLTAGE_MODE_CONFIGR/W0h Voltage mode configuration for reference profiles
  • 0h = User defined reference modes throughout the duty range
  • 1h = Voltage mode if input duty > DUTY_C + DUTY_HYST; configured reference mode if input duty < DUTY_C - DUTY_HYST
  • 2h = configured reference mode if input duty > DUTY_C + DUTY_HYST; voltage mode if input duty < DUTY_C - DUTY_HYST
  • 3h = Not Applicable
1DUTY_COMMAND_FILTERR/W0h Speed pin input filter
  • 0h = Filter on Speed pin is disabled
  • 1h = Filter on Speed pin is enabled (0.4%)
0RESERVEDR0h Reserved

8.1.14 REF_PROFILES6 Register (Offset = 9Eh) [Reset = 00000000h]

REF_PROFILES6 is shown in Figure 8-14 and described in Table 8-16.

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Register to configure Reference profile6

Figure 8-14 REF_PROFILES6 Register
3130292827262524
PARITYREF_OFF2
R-0hR/W-0h
2322212019181716
REF_OFF2REF_CLAMP2
R/W-0hR/W-0h
15141312111098
REF_CLAMP2RESERVED
R/W-0hR-0h
76543210
RESERVED
R-0h
Table 8-16 REF_PROFILES6 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR0h Parity bit
30-23REF_OFF2R/W0h Turn off Ref (% of Maximum Reference)) = {(REF_OFF2/256)*100}
22-15REF_CLAMP2R/W0h Clamp Ref 2 (% of Maximum Reference) = {(REF_CLAMP2/256)*100}
14-0RESERVEDR0h Reserved