SLLSFX9A December   2024  – May 2025 MCF8316D

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Output Stage
      2. 7.3.2  Device Interface
        1. 7.3.2.1 Interface - Control and Monitoring
        2. 7.3.2.2 I2C Interface
      3. 7.3.3  Step-Down Mixed-Mode Buck Regulator
        1. 7.3.3.1 Buck in Inductor Mode
        2. 7.3.3.2 Buck in Resistor mode
        3. 7.3.3.3 Buck Regulator with External LDO
        4. 7.3.3.4 AVDD Power Sequencing from Buck Regulator
        5. 7.3.3.5 Mixed Mode Buck Operation and Control
      4. 7.3.4  AVDD Linear Voltage Regulator
      5. 7.3.5  Charge Pump
      6. 7.3.6  Slew Rate Control
      7. 7.3.7  Cross Conduction (Dead Time)
      8. 7.3.8  Motor Control Input Sources
        1. 7.3.8.1 Analog-Mode Motor Control
        2. 7.3.8.2 PWM-Mode Motor Control
        3. 7.3.8.3 I2C-based Motor Control
        4. 7.3.8.4 Frequency-Mode Motor Control
        5. 7.3.8.5 Input Reference Profiles
          1. 7.3.8.5.1 Linear Control Profiles
          2. 7.3.8.5.2 Staircase Control Profiles
          3. 7.3.8.5.3 Forward-Reverse Profiles
          4. 7.3.8.5.4 Multi-Reference Mode Operation
          5. 7.3.8.5.5 Input Reference Transfer Function without Profiler
      9. 7.3.9  Starting the Motor Under Different Initial Conditions
        1. 7.3.9.1 Case 1 – Motor is Stationary
        2. 7.3.9.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 7.3.9.3 Case 3 – Motor is Spinning in the Reverse Direction
      10. 7.3.10 Motor Start Sequence (MSS)
        1. 7.3.10.1 Initial Speed Detect (ISD)
        2. 7.3.10.2 Motor Resynchronization
        3. 7.3.10.3 Reverse Drive
          1. 7.3.10.3.1 Reverse Drive Tuning
        4. 7.3.10.4 Motor Start-up
          1. 7.3.10.4.1 Align
          2. 7.3.10.4.2 Double Align
          3. 7.3.10.4.3 Initial Position Detection (IPD)
            1. 7.3.10.4.3.1 IPD Operation
            2. 7.3.10.4.3.2 IPD Release Mode
            3. 7.3.10.4.3.3 IPD Advance Angle
          4. 7.3.10.4.4 Slow First Cycle Startup
          5. 7.3.10.4.5 Open Loop
          6. 7.3.10.4.6 Transition from Open to Closed Loop
      11. 7.3.11 Closed Loop Operation
        1. 7.3.11.1 Closed Loop Acceleration/Deceleration Slew Rate
        2. 7.3.11.2 Speed PI Control
        3. 7.3.11.3 Current PI Control
        4. 7.3.11.4 Power Control Mode
        5. 7.3.11.5 Current (Torque) Control Mode
        6. 7.3.11.6 Modulation Index Control
        7. 7.3.11.7 Overmodulation
        8. 7.3.11.8 Motor Speed Limit
        9. 7.3.11.9 Input DC Power Limit
      12. 7.3.12 Flux Weakening Control
      13. 7.3.13 Motor Parameters
        1. 7.3.13.1 Motor Resistance
        2. 7.3.13.2 Motor Inductance
        3. 7.3.13.3 Motor Back-EMF constant
      14. 7.3.14 Motor Parameter Extraction Tool (MPET)
      15. 7.3.15 Anti-Voltage Surge (AVS)
      16. 7.3.16 Active Braking
      17. 7.3.17 Output PWM Switching Frequency
      18. 7.3.18 PWM Dithering
      19. 7.3.19 PWM Modulation Schemes
      20. 7.3.20 Dead Time Compensation
      21. 7.3.21 Motor Stop Options
        1. 7.3.21.1 Coast (Hi-Z) Mode
        2. 7.3.21.2 Recirculation Mode
        3. 7.3.21.3 Low-Side Braking
        4. 7.3.21.4 High-Side Braking
        5. 7.3.21.5 Active Spin-Down
      22. 7.3.22 Align Braking
      23. 7.3.23 FG Configuration
        1. 7.3.23.1 FG Output Frequency
        2. 7.3.23.2 FG during Open and Closed Loop States
        3. 7.3.23.3 FG during Fault and Idle States
      24. 7.3.24 Protections
        1. 7.3.24.1  VM Supply Undervoltage Lockout
        2. 7.3.24.2  AVDD Undervoltage Lockout (AVDD_UV)
        3. 7.3.24.3  BUCK Under Voltage Lockout (BUCK_UV)
        4. 7.3.24.4  VCP Charge Pump Undervoltage Lockout (CPUV)
        5. 7.3.24.5  Overvoltage Protection (OVP)
        6. 7.3.24.6  Overcurrent Protection (OCP)
          1. 7.3.24.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
          2. 7.3.24.6.2 OCP Automatic Retry (OCP_MODE = 01b)
        7. 7.3.24.7  Buck Overcurrent Protection
        8. 7.3.24.8  Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)
          1. 7.3.24.8.1 HW_LOCK_ILIMIT Latched Shutdown
          2. 7.3.24.8.2 HW_LOCK_ILIMIT Automatic Recovery
          3. 7.3.24.8.3 HW_LOCK_ILIMIT Report Only
          4. 7.3.24.8.4 HW_LOCK_ILIMIT Disabled
        9. 7.3.24.9  Lock Detection Current Limit (LOCK_ILIMIT)
          1. 7.3.24.9.1 LOCK_ILIMIT Latched Shutdown
          2. 7.3.24.9.2 LOCK_ILIMIT Automatic Recovery
          3. 7.3.24.9.3 LOCK_ILIMIT Report Only
          4. 7.3.24.9.4 LOCK_ILIMIT Disabled
        10. 7.3.24.10 Motor Lock Detection
          1. 7.3.24.10.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 7.3.24.10.2 Lock 2: Abnormal BEMF (ABN_BEMF)
          3. 7.3.24.10.3 Lock3: No-Motor Fault (NO_MTR)
        11. 7.3.24.11 Motor Lock (MTR_LCK)
          1. 7.3.24.11.1 MTR_LCK Latched Shutdown
          2. 7.3.24.11.2 MTR_LCK Automatic Recovery
          3. 7.3.24.11.3 MTR_LCK Report Only
          4. 7.3.24.11.4 MTR_LCK Disabled
        12. 7.3.24.12 EEPROM Fault
        13. 7.3.24.13 I2C CRC Fault
        14. 7.3.24.14 Minimum VM (Undervoltage) Protection
        15. 7.3.24.15 Maximum VM (Overvoltage) Protection
        16. 7.3.24.16 MPET Faults
        17. 7.3.24.17 IPD Faults
        18. 7.3.24.18 FET Thermal Warning (OTW)
        19. 7.3.24.19 FET Thermal Shutdown (TSD_FET)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Standby Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT)
    5. 7.5 External Interface
      1. 7.5.1 DRVOFF Functionality
      2. 7.5.2 DAC outputs
      3. 7.5.3 Current Sense Output
      4. 7.5.4 Oscillator Source
        1. 7.5.4.1 External Clock Source
      5. 7.5.5 External Watchdog
    6. 7.6 EEPROM access and I2C interface
      1. 7.6.1 EEPROM Access
        1. 7.6.1.1 EEPROM Write
        2. 7.6.1.2 EEPROM Read
        3. 7.6.1.3 EEPROM Security
      2. 7.6.2 I2C Serial Interface
        1. 7.6.2.1 I2C Data Word
        2. 7.6.2.2 I2C Write Transaction
        3. 7.6.2.3 I2C Read Transaction
        4. 7.6.2.4 I2C Communication Protocol Packet Examples
        5. 7.6.2.5 I2C Clock Stretching
        6. 7.6.2.6 CRC Byte Calculation
  9. 8 EEPROM (Non-Volatile) Register Map
    1. 8.1 Algorithm_Configuration Registers
    2. 8.2 Fault_Configuration Registers
    3. 8.3 Hardware_Configuration Registers
    4. 8.4 Internal_Algorithm_Configuration Registers
  10. 9 RAM (Volatile) Register Map
    1. 9.1 Fault_Status Registers
    2. 9.2 System_Status Registers
    3. 9.3 Device_Control Registers
    4. 9.4 Algorithm_Control Registers
    5. 9.5 Algorithm_Variables Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Application Curves
        1. 10.2.1.1 Motor startup
        2. 10.2.1.2 MPET
        3. 10.2.1.3 Dead time compensation
        4. 10.2.1.4 Auto handoff
        5. 10.2.1.5 Anti voltage surge (AVS)
        6. 10.2.1.6 Real time variable tracking using DACOUT
    3. 10.3 UL Recognized Component: MCF8316DULVRGFR
      1. 10.3.1 IEC 60730 Functional Safety System
      2. 10.3.2 IEC 60730 Self Test Library (available only in MCF8316DULVRGFR)
    4. 10.4 Power Supply Recommendations
      1. 10.4.1 Bulk Capacitance
    5. 10.5 Layout
      1. 10.5.1 Layout Guidelines
      2. 10.5.2 Layout Example
      3. 10.5.3 Thermal Considerations
        1. 10.5.3.1 Power Dissipation
  12. 11Device and Documentation Support
    1. 11.1 Support Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

8.3 Hardware_Configuration Registers

Table 8-21 lists the memory-mapped registers for the Hardware_Configuration registers. All register offset addresses not listed in Table 8-21 should be considered as reserved locations and the register contents should not be modified.

Table 8-21 HARDWARE_CONFIGURATION Registers
OffsetAcronymRegister NameSection
A4hPIN_CONFIGHardware Pin ConfigurationSection 8.3.1
A6hDEVICE_CONFIG1Device configuration1Section 8.3.2
A8hDEVICE_CONFIG2Device configuration2Section 8.3.3
AAhPERI_CONFIG1Peripheral Configuration1Section 8.3.4
AChGD_CONFIG1Gate Driver Configuration1Section 8.3.5
AEhGD_CONFIG2Gate Driver Configuration2Section 8.3.6

Complex bit access types are encoded to fit into small table cells. Table 8-22 shows the codes that are used for access types in this section.

Table 8-22 Hardware_Configuration Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

8.3.1 PIN_CONFIG Register (Offset = A4h) [Reset = 00000000h]

PIN_CONFIG is shown in Figure 8-17 and described in Table 8-23.

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Register to configure hardware pins

Figure 8-17 PIN_CONFIG Register
3130292827262524
PARITYPWM_DITHER_STEPVDC_FILTERLEAD_ANGLE
R-0hR/W-0hR/W-0hR/W-0h
2322212019181716
LEAD_ANGLEMAX_POWER
R/W-0hR/W-0h
15141312111098
MAX_POWERFG_IDLE_CONFIGFG_FAULT_CONFIG
R/W-0hR/W-0hR/W-0h
76543210
FG_FAULT_CONFIGALARM_PIN_ENBRAKE_PIN_MODEALIGN_BRAKE_ANGLE_SELBRAKE_INPUTSPEED_MODE
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 8-23 PIN_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR0h Parity bit
30-29PWM_DITHER_STEPR/W0h PWM dither slew rate
  • 0h = 1
  • 1h = 2
  • 2h = 5
  • 3h = 10
28-27VDC_FILTERR/W0h Vdc(VM) filter coefficient
  • 0h = Disable
  • 1h = Enable with default filter cut-off frequency
  • 2h = Enable with filter cut-off frequency 100Hz
  • 3h = Enable with filter cut-off frequency 1000Hz
26-22LEAD_ANGLER/W0h Lead angle. In voltage mode, positive value indicates the applied voltage is leading the BEMF, negative value indicates applied voltage is lagging the BEMF. In other modes, positive means negative id reference, negative means positive id reference
  • 0h = 0 deg
  • 1h = 3 deg
  • 2h = 6 deg
  • 3h = 9 deg
  • 4h = 12 deg
  • 5h = 15 deg
  • 6h = 18 deg
  • 7h = 21 deg
  • 8h = 24 deg
  • 9h = 27 deg
  • Ah = 30 deg
  • Bh = 33 deg
  • Ch = 36 deg
  • Dh = 39 deg
  • Eh = 42 deg
  • Fh = 45 deg
  • 10h = -48 deg
  • 11h = -45 deg
  • 12h = -42 deg
  • 13h = -39 deg
  • 14h = -36 deg
  • 15h = -33 deg
  • 16h = -30 deg
  • 17h = -27 deg
  • 18h = -24 deg
  • 19h = -21 deg
  • 1Ah = -18 deg
  • 1Bh = -15 deg
  • 1Ch = -12 deg
  • 1Dh = -9 deg
  • 1Eh = -6 deg
  • 1Fh = -3 deg
21-11MAX_POWERR/W0h Maximum power for power loop or power limit. Max power in Watts = (MAX_POWER / 211) * 100
10-9FG_IDLE_CONFIGR/W0h FG configuration during motor stopped/idle state
  • 0h = FG continues and end state depends on FG_CONFIG and last state before motor stops
  • 1h = FG is pulled High
  • 2h = FG is pulled Low
  • 3h = FG is pulled High
8-7FG_FAULT_CONFIGR/W0h FG configuration during fault state. BEMF threshold defined by FG_BEMF_THR if FG_CONFIG 1
  • 0h = Use last FG signal when motor was driven
  • 1h = FG is pulled High
  • 2h = FG is pulled Low
  • 3h = FG active till BEMF drops below BEMF threshold
6ALARM_PIN_ENR/W0h Enable Alarm pin
  • 0h = Disable
  • 1h = Enable
5BRAKE_PIN_MODER/W0h Brake pin mode
  • 0h = Low side Brake
  • 1h = Align Brake
4ALIGN_BRAKE_ANGLE_SELR/W0h Select align brake angle
  • 0h = Use last commutation angle before entering align braking
  • 1h = Use ALIGN_ANGLE configuration for align braking
3-2BRAKE_INPUTR/W0h Brake pin override
  • 0h = Hardware Pin BRAKE
  • 1h = Override pin and brake / align according to BRAKE_PIN_MODE
  • 2h = Override pin and do not brake / align
  • 3h = Hardware Pin BRAKE
1-0SPEED_MODER/W0h Configure motor control input source
  • 0h = Controlled by analog voltage on SPEED pin
  • 1h = Controlled by duty cycle (PWM) on SPEED pin
  • 2h = Controlled by DIGITAL_SPEED_CTRL value (I2C)
  • 3h = Controlled by frequency on SPEED pin

8.3.2 DEVICE_CONFIG1 Register (Offset = A6h) [Reset = 00000000h]

DEVICE_CONFIG1 is shown in Figure 8-18 and described in Table 8-24.

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Register to configure device

Figure 8-18 DEVICE_CONFIG1 Register
3130292827262524
PARITYRESERVEDDAC_SOx_SELPWM_DITHER_MODEI2C_TARGET_ADDR
R-0hR-0hR/W-0hR/W-0hR/W-0h
2322212019181716
I2C_TARGET_ADDREEPROM_LOCK_KEY
R/W-0hR/W-0h
15141312111098
EEPROM_LOCK_KEY
R/W-0h
76543210
EEPROM_LOCK_KEYSLEW_RATE_I2C_PINSPULLUP_ENABLEBUS_VOLT
R/W-0hR/W-0hR/W-0hR/W-0h
Table 8-24 DEVICE_CONFIG1 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR0h Parity bit
30RESERVEDR0h Reserved
29-28DAC_SOx_SELR/W0h Select between DACOUT2 and SOx channels
  • 0h = DACOUT2
  • 1h = SOA
  • 2h = SOB
  • 3h = SOC
27PWM_DITHER_MODER/W0h PWM dither mode
  • 0h = Triangular Mode
  • 1h = Random Mode
26-20I2C_TARGET_ADDRR/W0h I2C target address
19-5EEPROM_LOCK_KEYR/W0h EEPROM lock/unlock key when EEPROM R/W protection is enabled. This bitfield will always read 0 when read.
4-3SLEW_RATE_I2C_PINSR/W0h Slew rate control for I2C pins
  • 0h = 4.8 mA
  • 1h = 3.9 mA
  • 2h = 1.86 mA
  • 3h = 30.8 mA
2PULLUP_ENABLER/W0h Internal pull-up enable for nFAULT and FG pins
  • 0h = Disable
  • 1h = Enable
1-0BUS_VOLTR/W0h Maximum DC bus voltage configuration
  • 0h = 15 V
  • 1h = 30 V
  • 2h = 40 V
  • 3h = Not Applicable

8.3.3 DEVICE_CONFIG2 Register (Offset = A8h) [Reset = 00000000h]

DEVICE_CONFIG2 is shown in Figure 8-19 and described in Table 8-25.

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Register to configure device

Figure 8-19 DEVICE_CONFIG2 Register
3130292827262524
PARITYINPUT_MAXIMUM_FREQ
R-0hR/W-0h
2322212019181716
INPUT_MAXIMUM_FREQ
R/W-0h
15141312111098
SLEEP_ENTRY_TIMEDYNAMIC_CSA_GAIN_ENDYNAMIC_VOLTAGE_GAIN_ENDEV_MODEPWM_DITHER_DEPTHEXT_CLK_EN
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
EXT_CLK_CONFIGEXT_WDT_ENEXT_WDT_CONFIGEXT_WDT_INPUT_MODEEXT_WDT_FAULT_MODE
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 8-25 DEVICE_CONFIG2 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR0h Parity bit
30-16INPUT_MAXIMUM_FREQR/W0h Input frequency on speed pin for input reference mode as "controlled by frequency of SPEED pin" that corresponds to 100% duty cycle. Duty cycle = Input frequency / INPUT_MAXIMUM_FREQ
15-14SLEEP_ENTRY_TIMER/W0h Device enters sleep mode when input source (SPEED_MODE) is held at or below the sleep entry threshold for SLEEP_ENTRY_TIME
  • 0h = Sleep Entry when SPEED pin remains low for 50 µs
  • 1h = Sleep Entry when SPEED pin remains low for 200 µs
  • 2h = Sleep Entry when SPEED pin remains low for 20 ms
  • 3h = Sleep Entry when SPEED pin remains low for 200 ms
13DYNAMIC_CSA_GAIN_ENR/W0h Adjust CSA gain automatically for optimal current resolution at all current levels
  • 0h = Disable
  • 1h = Enable
12DYNAMIC_VOLTAGE_GAIN_ENR/W0h Adjust voltage gain automatically for optimal voltage resolution at all voltage levels
  • 0h = Disable
  • 1h = Enable
11DEV_MODER/W0h Device mode select
  • 0h = Standby Mode
  • 1h = Sleep Mode
10-9PWM_DITHER_DEPTHR/W0h PWM dither depth
  • 0h = PWM dither disabled
  • 1h = 5%
  • 2h = 7.5%
  • 3h = 10%
8EXT_CLK_ENR/W0h Enable external clock mode
  • 0h = Disable
  • 1h = Enable
7-5EXT_CLK_CONFIGR/W0h External clock frequency configuration
  • 0h = 8 kHz
  • 1h = 16 kHz
  • 2h = 32 kHz
  • 3h = 64 kHz
  • 4h = 128 kHz
  • 5h = 256 kHz
  • 6h = 512 kHz
  • 7h = 1024 kHz
4EXT_WDT_ENR/W0h Enable external watchdog
  • 0h = Disable
  • 1h = Enable
3-2EXT_WDT_CONFIGR/W0h Time between watchdog tickles (GPIO/I2C)
  • 0h = 100ms/1s
  • 1h = 200ms/2s
  • 2h = 500ms/5s
  • 3h = 1000ms/10s
1EXT_WDT_INPUT_MODER/W0h External watchdog input source
  • 0h = Watchdog tickle over I2C
  • 1h = Watchdog tickle over GPIO
0EXT_WDT_FAULT_MODER/W0h External watchdog fault mode
  • 0h = Report only
  • 1h = Latch with MOSFETs in Hi-Z

8.3.4 PERI_CONFIG1 Register (Offset = AAh) [Reset = 00000000h]

PERI_CONFIG1 is shown in Figure 8-20 and described in Table 8-26.

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Register to peripheral1

Figure 8-20 PERI_CONFIG1 Register
3130292827262524
PARITYSPREAD_SPECTRUM_MODULATION_DISRESERVEDNO_MTR_FLT_CLOSEDLOOP_DISABNORMAL_BEMF_PERSISTENT_TIMEFLUX_WEAK_REF
R-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0h
2322212019181716
INPUT_REFERENCE_WINDOWBUS_POWER_LIMIT_ENABLEDIR_INPUTDIR_CHANGE_MODESPEED_LIMIT_ENABLEACTIVE_BRAKE_SPEED_DELTA_LIMIT_ENTRY
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
ACTIVE_BRAKE_SPEED_DELTA_LIMIT_ENTRYACTIVE_BRAKE_MOD_INDEX_LIMITSPEED_RANGE_SELINPUT_REFERENCE_MODE
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
INPUT_REFERENCE_MODEEEPROM_LOCK_MODERESERVED
R/W-0hR/W-0hR-0h
Table 8-26 PERI_CONFIG1 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR0h Parity bit
30SPREAD_SPECTRUM_MODULATION_DISR/W0h Disable Spread Spectrum Modulation (SSM)
  • 0h = SSM is Enabled
  • 1h = SSM is Disabled
29RESERVEDR0h Reserved
28NO_MTR_FLT_CLOSEDLOOP_DISR/W0h Disable No Motor fault in closed loop
  • 0h = Enable no motor fault in closed loop if LOCK2_EN is set to 0x1
  • 1h = Disable No Motor fault in closed loop
27-26ABNORMAL_BEMF_PERSISTENT_TIMER/W0h Deglitch time for Abnormal BEMF fault detection
  • 0h = 2 electrical cycles
  • 1h = 500 ms
  • 2h = 1000 ms
  • 3h = 2000 ms
25-24FLUX_WEAK_REFR/W0h Reference for flux weakening controller
  • 0h = 70%
  • 1h = 80%
  • 2h = 90%
  • 3h = 95%
23-22INPUT_REFERENCE_WINDOWR/W0h Disables all control loops when output reaches within the window
  • 0h = Reference window disabled
  • 1h = Reference window of 5%
  • 2h = Reference window of 10%
  • 3h = Reference window of 15%
21BUS_POWER_LIMIT_ENABLER/W0h Enable bus power limit. Limits input DC bus power to MAX_POWER in all input reference modes except power mode
  • 0h = Disable power limit
  • 1h = Enable power limit
20-19DIR_INPUTR/W0h DIR pin override
  • 0h = Hardware Pin DIR
  • 1h = Override DIR pin with clockwise rotation OUTA-OUTB-OUTC
  • 2h = Override DIR pin with counter clockwise rotation OUTA-OUTC-OUTB
  • 3h = Hardware Pin DIR
18DIR_CHANGE_MODER/W0h Response to change of DIR pin status
  • 0h = Follow motor stop options and ISD routine on detecting DIR change
  • 1h = Change the direction through Reverse Drive while continuously driving the motor
17SPEED_LIMIT_ENABLER/W0h Enable motor speed limit. Limits motor speed to MAX_SPEED in all input reference modes except speed mode
  • 0h = Disable speed limit
  • 1h = Enable speed limit
16-13ACTIVE_BRAKE_SPEED_DELTA_LIMIT_ENTRYR/W0h Difference between final speed and present speed below which active braking will be applied
  • 0h = Not Applicable
  • 1h = 5%
  • 2h = 10%
  • 3h = 15%
  • 4h = 20%
  • 5h = 25%
  • 6h = 30%
  • 7h = 35%
  • 8h = 40%
  • 9h = 45%
  • Ah = 50%
  • Bh = 60%
  • Ch = 70%
  • Dh = 80%
  • Eh = 90%
  • Fh = 100%
12-10ACTIVE_BRAKE_MOD_INDEX_LIMITR/W0h Modulation index limit below which active braking will be applied
  • 0h = 0%
  • 1h = 40%
  • 2h = 50%
  • 3h = 60%
  • 4h = 70%
  • 5h = 80%
  • 6h = 90%
  • 7h = 100%
9SPEED_RANGE_SELR/W0h Frequency range selection for PWM duty mode reference input
  • 0h = 325Hz to 100kHz
  • 1h = 10Hz to 325Hz
8-7INPUT_REFERENCE_MODER/W0h Input reference mode used for close loop operation
  • 0h = Control speed (Input is speed reference, scaled to MAX_SPEED)
  • 1h = Control power (Input is power reference, scaled to MAX_POWER)
  • 2h = Control Torque (Input is current reference, scaled to ILIMIT)
  • 3h = Control Modulation Index (Input is modulation index scaled to 100%)
6-5EEPROM_LOCK_MODER/W0h EEPROM lock mode
  • 0h = EEPROM read and write allowed without a passcode
  • 1h = EEPROM read and write need a valid passcode
  • 2h = EEPROM read needs a valid passcode, write is locked permanently
  • 3h = EEPROM read and write is locked permanently
4-0RESERVEDR0h Reserved

8.3.5 GD_CONFIG1 Register (Offset = ACh) [Reset = 00000000h]

GD_CONFIG1 is shown in Figure 8-21 and described in Table 8-27.

Return to the Summary Table.

Register to configure gated driver settings1

Figure 8-21 GD_CONFIG1 Register
3130292827262524
PARITYRESERVEDRESERVEDSLEW_RATERESERVED
R-0hR-0hR-0hR/W-0hR-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDOVP_SELOVP_ENRESERVEDOTW_REP
R-0hR-0hR-0hR-0hR/W-0hR/W-0hR-0hR/W-0h
15141312111098
RESERVEDRESERVEDOCP_DEGRESERVEDOCP_LVLOCP_MODE
R-0hR-0hR/W-0hR-0hR/W-0hR/W-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDCSA_GAIN
R-0hR-0hR-0hR-0hR-0hR-0hR/W-0h
Table 8-27 GD_CONFIG1 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR0h Parity bit
30-29RESERVEDR0h Reserved
28RESERVEDR0h Reserved
27-26SLEW_RATER/W0h Slew rate
  • 0h = Not Applicable
  • 1h = Not Applicable
  • 2h = Slew rate is 125 V/µs
  • 3h = Slew rate is 200 V/µs
25-24RESERVEDR0h Reserved
23RESERVEDR0h Reserved
22RESERVEDR0h Reserved
21RESERVEDR0h Reserved
20RESERVEDR0h Reserved
19OVP_SELR/W0h Overvoltage level
  • 0h = VM overvoltage level is 34-V
  • 1h = VM overvoltage level is 22-V
18OVP_ENR/W0h Enable overvoltage
  • 0h = Overvoltage protection is disabled
  • 1h = Overvoltage protection is enabled
17RESERVEDR0h Reserved
16OTW_REPR/W0h Overtemperature warning reporting
  • 0h = Over temperature warning reporting is disabled
  • 1h = Over temperature warning reporting is enabled
15RESERVEDR0h Reserved
14RESERVEDR0h Reserved
13-12OCP_DEGR/W0h OCP deglitch time
  • 0h = OCP deglitch time is 0.2 µs
  • 1h = OCP deglitch time is 0.6 µs
  • 2h = OCP deglitch time is 1.2 µs
  • 3h = OCP deglitch time is 1.6 µs
11RESERVEDR0h Reserved
10OCP_LVLR/W0h Overcurrent level
  • 0h = OCP level is 16 A (Typical)
  • 1h = OCP level is 24 A (Typical)
9-8OCP_MODER/W0h OCP fault mode
  • 0h = Overcurrent causes a latched fault
  • 1h = Overcurrent causes an automatic retry after 500ms
  • 2h = Not Applicable
  • 3h = Not Applicable
7RESERVEDR0h Reserved
6RESERVEDR0h Reserved
5RESERVEDR0h Reserved
4RESERVEDR0h Reserved
3RESERVEDR0h Reserved
2RESERVEDR0h Reserved
1-0CSA_GAINR/W0h Current sense amplifier's gain (used only if DYNAMIC_CSA_GAIN_EN = 0x0)
  • 0h = CSA gain is 0.15 V/A
  • 1h = CSA gain is 0.3 V/A
  • 2h = CSA gain is 0.6 V/A
  • 3h = CSA gain is 1.2 V/A

8.3.6 GD_CONFIG2 Register (Offset = AEh) [Reset = 00000000h]

GD_CONFIG2 is shown in Figure 8-22 and described in Table 8-28.

Return to the Summary Table.

Register to configure gated driver settings2

Figure 8-22 GD_CONFIG2 Register
3130292827262524
PARITYRESERVEDRESERVEDRESERVEDBUCK_PS_DIS
R-0hR-0hR-0hR-0hR/W-0h
2322212019181716
BUCK_CLBUCK_SELBUCK_DISMIN_ON_TIMERESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR-0h
15141312111098
RESERVEDRESERVED
R-0hR-0h
76543210
RESERVED
R-0h
Table 8-28 GD_CONFIG2 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR0h Parity bit
30RESERVEDR0h Reserved
29-26RESERVEDR0h Reserved
25RESERVEDR0h Reserved
24BUCK_PS_DISR/W0h Buck power sequencing disable
  • 0h = Buck power sequencing is enabled
  • 1h = Buck power sequencing is disabled
23BUCK_CLR/W0h Buck current limit
  • 0h = Buck regulator current limit is set to 600 mA
  • 1h = Buck regulator current limit is set to 150 mA
22-21BUCK_SELR/W0h Buck output voltage
  • 0h = Buck voltage is 3.3 V
  • 1h = Buck voltage is 5.0 V
  • 2h = Buck voltage is 4.0 V
  • 3h = Buck voltage is 5.7 V
20BUCK_DISR/W0h Buck disable
  • 0h = Buck regulator is enabled
  • 1h = Buck regulator is disabled
19-17MIN_ON_TIMER/W0h Minimum ON time for low side MOSFET
  • 0h = 0 µs
  • 1h = Automatic based on slew rate
  • 2h = 0.5 µs
  • 3h = 0.75 µs
  • 4h = 1 µs
  • 5h = 1.25 µs
  • 6h = 1.5 µs
  • 7h = 2 µs
16-13RESERVEDR0h Reserved
12-0RESERVEDR0h Reserved