SLLSFX9A December   2024  – May 2025 MCF8316D

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Output Stage
      2. 7.3.2  Device Interface
        1. 7.3.2.1 Interface - Control and Monitoring
        2. 7.3.2.2 I2C Interface
      3. 7.3.3  Step-Down Mixed-Mode Buck Regulator
        1. 7.3.3.1 Buck in Inductor Mode
        2. 7.3.3.2 Buck in Resistor mode
        3. 7.3.3.3 Buck Regulator with External LDO
        4. 7.3.3.4 AVDD Power Sequencing from Buck Regulator
        5. 7.3.3.5 Mixed Mode Buck Operation and Control
      4. 7.3.4  AVDD Linear Voltage Regulator
      5. 7.3.5  Charge Pump
      6. 7.3.6  Slew Rate Control
      7. 7.3.7  Cross Conduction (Dead Time)
      8. 7.3.8  Motor Control Input Sources
        1. 7.3.8.1 Analog-Mode Motor Control
        2. 7.3.8.2 PWM-Mode Motor Control
        3. 7.3.8.3 I2C-based Motor Control
        4. 7.3.8.4 Frequency-Mode Motor Control
        5. 7.3.8.5 Input Reference Profiles
          1. 7.3.8.5.1 Linear Control Profiles
          2. 7.3.8.5.2 Staircase Control Profiles
          3. 7.3.8.5.3 Forward-Reverse Profiles
          4. 7.3.8.5.4 Multi-Reference Mode Operation
          5. 7.3.8.5.5 Input Reference Transfer Function without Profiler
      9. 7.3.9  Starting the Motor Under Different Initial Conditions
        1. 7.3.9.1 Case 1 – Motor is Stationary
        2. 7.3.9.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 7.3.9.3 Case 3 – Motor is Spinning in the Reverse Direction
      10. 7.3.10 Motor Start Sequence (MSS)
        1. 7.3.10.1 Initial Speed Detect (ISD)
        2. 7.3.10.2 Motor Resynchronization
        3. 7.3.10.3 Reverse Drive
          1. 7.3.10.3.1 Reverse Drive Tuning
        4. 7.3.10.4 Motor Start-up
          1. 7.3.10.4.1 Align
          2. 7.3.10.4.2 Double Align
          3. 7.3.10.4.3 Initial Position Detection (IPD)
            1. 7.3.10.4.3.1 IPD Operation
            2. 7.3.10.4.3.2 IPD Release Mode
            3. 7.3.10.4.3.3 IPD Advance Angle
          4. 7.3.10.4.4 Slow First Cycle Startup
          5. 7.3.10.4.5 Open Loop
          6. 7.3.10.4.6 Transition from Open to Closed Loop
      11. 7.3.11 Closed Loop Operation
        1. 7.3.11.1 Closed Loop Acceleration/Deceleration Slew Rate
        2. 7.3.11.2 Speed PI Control
        3. 7.3.11.3 Current PI Control
        4. 7.3.11.4 Power Control Mode
        5. 7.3.11.5 Current (Torque) Control Mode
        6. 7.3.11.6 Modulation Index Control
        7. 7.3.11.7 Overmodulation
        8. 7.3.11.8 Motor Speed Limit
        9. 7.3.11.9 Input DC Power Limit
      12. 7.3.12 Flux Weakening Control
      13. 7.3.13 Motor Parameters
        1. 7.3.13.1 Motor Resistance
        2. 7.3.13.2 Motor Inductance
        3. 7.3.13.3 Motor Back-EMF constant
      14. 7.3.14 Motor Parameter Extraction Tool (MPET)
      15. 7.3.15 Anti-Voltage Surge (AVS)
      16. 7.3.16 Active Braking
      17. 7.3.17 Output PWM Switching Frequency
      18. 7.3.18 PWM Dithering
      19. 7.3.19 PWM Modulation Schemes
      20. 7.3.20 Dead Time Compensation
      21. 7.3.21 Motor Stop Options
        1. 7.3.21.1 Coast (Hi-Z) Mode
        2. 7.3.21.2 Recirculation Mode
        3. 7.3.21.3 Low-Side Braking
        4. 7.3.21.4 High-Side Braking
        5. 7.3.21.5 Active Spin-Down
      22. 7.3.22 Align Braking
      23. 7.3.23 FG Configuration
        1. 7.3.23.1 FG Output Frequency
        2. 7.3.23.2 FG during Open and Closed Loop States
        3. 7.3.23.3 FG during Fault and Idle States
      24. 7.3.24 Protections
        1. 7.3.24.1  VM Supply Undervoltage Lockout
        2. 7.3.24.2  AVDD Undervoltage Lockout (AVDD_UV)
        3. 7.3.24.3  BUCK Under Voltage Lockout (BUCK_UV)
        4. 7.3.24.4  VCP Charge Pump Undervoltage Lockout (CPUV)
        5. 7.3.24.5  Overvoltage Protection (OVP)
        6. 7.3.24.6  Overcurrent Protection (OCP)
          1. 7.3.24.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
          2. 7.3.24.6.2 OCP Automatic Retry (OCP_MODE = 01b)
        7. 7.3.24.7  Buck Overcurrent Protection
        8. 7.3.24.8  Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)
          1. 7.3.24.8.1 HW_LOCK_ILIMIT Latched Shutdown
          2. 7.3.24.8.2 HW_LOCK_ILIMIT Automatic Recovery
          3. 7.3.24.8.3 HW_LOCK_ILIMIT Report Only
          4. 7.3.24.8.4 HW_LOCK_ILIMIT Disabled
        9. 7.3.24.9  Lock Detection Current Limit (LOCK_ILIMIT)
          1. 7.3.24.9.1 LOCK_ILIMIT Latched Shutdown
          2. 7.3.24.9.2 LOCK_ILIMIT Automatic Recovery
          3. 7.3.24.9.3 LOCK_ILIMIT Report Only
          4. 7.3.24.9.4 LOCK_ILIMIT Disabled
        10. 7.3.24.10 Motor Lock Detection
          1. 7.3.24.10.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 7.3.24.10.2 Lock 2: Abnormal BEMF (ABN_BEMF)
          3. 7.3.24.10.3 Lock3: No-Motor Fault (NO_MTR)
        11. 7.3.24.11 Motor Lock (MTR_LCK)
          1. 7.3.24.11.1 MTR_LCK Latched Shutdown
          2. 7.3.24.11.2 MTR_LCK Automatic Recovery
          3. 7.3.24.11.3 MTR_LCK Report Only
          4. 7.3.24.11.4 MTR_LCK Disabled
        12. 7.3.24.12 EEPROM Fault
        13. 7.3.24.13 I2C CRC Fault
        14. 7.3.24.14 Minimum VM (Undervoltage) Protection
        15. 7.3.24.15 Maximum VM (Overvoltage) Protection
        16. 7.3.24.16 MPET Faults
        17. 7.3.24.17 IPD Faults
        18. 7.3.24.18 FET Thermal Warning (OTW)
        19. 7.3.24.19 FET Thermal Shutdown (TSD_FET)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Standby Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT)
    5. 7.5 External Interface
      1. 7.5.1 DRVOFF Functionality
      2. 7.5.2 DAC outputs
      3. 7.5.3 Current Sense Output
      4. 7.5.4 Oscillator Source
        1. 7.5.4.1 External Clock Source
      5. 7.5.5 External Watchdog
    6. 7.6 EEPROM access and I2C interface
      1. 7.6.1 EEPROM Access
        1. 7.6.1.1 EEPROM Write
        2. 7.6.1.2 EEPROM Read
        3. 7.6.1.3 EEPROM Security
      2. 7.6.2 I2C Serial Interface
        1. 7.6.2.1 I2C Data Word
        2. 7.6.2.2 I2C Write Transaction
        3. 7.6.2.3 I2C Read Transaction
        4. 7.6.2.4 I2C Communication Protocol Packet Examples
        5. 7.6.2.5 I2C Clock Stretching
        6. 7.6.2.6 CRC Byte Calculation
  9. 8 EEPROM (Non-Volatile) Register Map
    1. 8.1 Algorithm_Configuration Registers
    2. 8.2 Fault_Configuration Registers
    3. 8.3 Hardware_Configuration Registers
    4. 8.4 Internal_Algorithm_Configuration Registers
  10. 9 RAM (Volatile) Register Map
    1. 9.1 Fault_Status Registers
    2. 9.2 System_Status Registers
    3. 9.3 Device_Control Registers
    4. 9.4 Algorithm_Control Registers
    5. 9.5 Algorithm_Variables Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Application Curves
        1. 10.2.1.1 Motor startup
        2. 10.2.1.2 MPET
        3. 10.2.1.3 Dead time compensation
        4. 10.2.1.4 Auto handoff
        5. 10.2.1.5 Anti voltage surge (AVS)
        6. 10.2.1.6 Real time variable tracking using DACOUT
    3. 10.3 UL Recognized Component: MCF8316DULVRGFR
      1. 10.3.1 IEC 60730 Functional Safety System
      2. 10.3.2 IEC 60730 Self Test Library (available only in MCF8316DULVRGFR)
    4. 10.4 Power Supply Recommendations
      1. 10.4.1 Bulk Capacitance
    5. 10.5 Layout
      1. 10.5.1 Layout Guidelines
      2. 10.5.2 Layout Example
      3. 10.5.3 Thermal Considerations
        1. 10.5.3.1 Power Dissipation
  12. 11Device and Documentation Support
    1. 11.1 Support Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

9.3 Device_Control Registers

Table 9-11 lists the memory-mapped registers for the Device_Control registers. All register offset addresses not listed in Table 9-11 should be considered as reserved locations and the register contents should not be modified.

Table 9-11 DEVICE_CONTROL Registers
OffsetAcronymRegister NameSection
EAhALGO_CTRL1Device Control RegisterSection 9.3.1

Complex bit access types are encoded to fit into small table cells. Table 9-12 shows the codes that are used for access types in this section.

Table 9-12 Device_Control Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

9.3.1 ALGO_CTRL1 Register (Offset = EAh) [Reset = 00000000h]

ALGO_CTRL1 is shown in Figure 9-7 and described in Table 9-13.

Return to the Summary Table.

Control settings

Figure 9-7 ALGO_CTRL1 Register
3130292827262524
EEPROM_WRTEEPROM_READCLR_FLTCLR_FLT_RETRY_COUNTEEPROM_WRITE_ACCESS_KEY
R/W-0hR/W-0hW-0hW-0hW-0h
2322212019181716
EEPROM_WRITE_ACCESS_KEYFORCED_ALIGN_ANGLE
W-0hR/W-0h
15141312111098
FORCED_ALIGN_ANGLEWATCHDOG_TICKLESTL_CMDSTL_KEY
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
STL_KEYRESERVED
R/W-0hR-0h
Table 9-13 ALGO_CTRL1 Register Field Descriptions
BitFieldTypeResetDescription
31EEPROM_WRTR/W0h Write the configuration from RAM/shadow to EEPROM
30EEPROM_READR/W0h Read the default configuration from EEPROM to RAM/shadow
29CLR_FLTW0h Clears all faults
28CLR_FLT_RETRY_COUNTW0h Clears automatic fault retry count
27-20EEPROM_WRITE_ACCESS_KEYW0h EEPROM write access key (0xA5)
19-11FORCED_ALIGN_ANGLER/W0h 9-bit value (in degrees) used during forced align state (applicable when FORCE_ALIGN_EN = 0x1) For example if FORCED_ALIGN_ANGLE value is 225 degrees then angle applied during Forced Align will be 225 degrees, similarly if FORCED_ALIGN_ANGLE value is 395 degrees then angle applied during Forced Align will be 395%360 which is 35 degrees Angle applied = (FORCED_ALIGN_ANGLE % 360)deg
10WATCHDOG_TICKLER/W0h RAM bit to tickle watchdog in I2C mode. 0x1 should be written to this bit by external controller every EXT_WDT_CFG. Device will reset this bit to 0x0.
9STL_CMDR/W0h Command to initiate self test (applicable to MCF8316DULVRGFR only)
8-1STL_KEYR/W0h Key(0xBE) to initiate self test on demand (applicable to MCF8316DULVRGFR only)
0RESERVEDR0h Reserved