SLLSFY7B November   2025  – August 2026 ISOW6441 , ISOW6442

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics - Power Converter
    10. 5.10 Supply Current Characteristics - Power Converter
    11. 5.11 Electrical Characteristics - Isolation Channel - VDD = 5V, VDDL = 5V, VISO=5V
    12. 5.12 Supply Current Characteristics - Isolation Channel - VDD = 5V,  VDDL = 5V, VISO = 5V
    13. 5.13 Electrical Characteristics - Isolation Channel - VDD = 5V, VDDL = 5V, VISO=3.3V
    14. 5.14 Supply Current Characteristics - Isolation Channel - VDD = 5V,  VDDL = 5V, VISO = 3.3V
    15. 5.15 Electrical Characteristics - Isolation Channel - VDD = 3.3V, VDDL = 3.3V, VISO = 3.3V
    16. 5.16 Supply Current Characteristics - Isolation Channel - VDD = 3.3V, VDDL = 3.3V, VISO = 3.3V
    17. 5.17 Electrical Characteristics - Isolation Channel - VDDL = 2.5V
    18. 5.18 Supply Current Characteristics - Isolation Channel - VDDL = 2.5V
    19. 5.19 Switching Characteristics - VDDL = 5V, VISO = 5V
    20. 5.20 Switching Characteristics - VDDL = 3.3V, VISO = 3.3V
    21. 5.21 Switching Characteristics - VDDL = 2.5V, VISO = 5V
    22. 5.22 Switching Characteristics - VDDL = 2.5V, VISO = 3.3V
    23. 5.23 Insulation Characteristics Curves
    24. 5.24 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Power Isolation
      2. 7.1.2 Signal Isolation
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Electromagnetic Compatibility (EMC) Considerations
      2. 7.3.2 Power-Up and Power-Down Behavior
      3. 7.3.3 Protection Features
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device I/O Schematics
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 PCB Material
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1.     PACKAGE OPTION ADDENDUM
    2. 11.1 Tape and Reel Information

5.6 Insulation Specifications

PARAMETER TEST CONDITIONS VALUE UNIT
GENERAL
CLR External clearance(1) Shortest terminal-to-terminal distance through air >8 mm
CPG External creepage(1) Shortest terminal-to-terminal distance across the package surface >8 mm
DTI Distance through the insulation (Minimum internal gap) Signal isolation > 17 µm
Transformer power isolation >100
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 > 600 V
Material group According to IEC 60664-1 I
Overvoltage category per IEC 60664-1 Rated mains voltage ≤ 300 VRMS I-IV
Rated mains voltage ≤ 600 VRMS I-IV
Rated mains voltage ≤ 1000 VRMS I-III
DIN EN IEC 60747-17 (VDE 0884-17)
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 848 VPK
VIOWM Maximum working isolation voltage AC voltage; Time dependent dielectric breakdown (TDDB) Test 600 VRMS
DC voltage 848 VDC
VIOTM Maximum transient isolation voltage VTEST = VIOTM; t = 60s (qualification);
VTEST = 1.2 × VIOTM; t = 1s (100% production)		 7071 VPK
VIMP Maximum impulse voltage ISOW644x(2) Tested in air, 1.2/50-μs waveform per IEC
62368-1		 8000 VPK
VIOSM Maximum surge isolation voltage ISOW644x(2) VIOSM ≥ 1.3 x VIMP; Tested in oil (qualification
test), 1.2/50-μs waveform per IEC 62368-1		 10400 VPK
qpd Apparent charge(3) Method a, after input/output safety test subgroup 2/3,
Vini = VIOTM, tini = 60s;
Vpd(m) = 1.2 × VIORM, tm = 10s		 ≤ 5 pC
Method a, after environmental tests subgroup 1,
Vini = VIOTM, tini = 60s; ISOW644x: Vpd(m) = 1.6 × VIORM, tm = 10s		 ≤ 5
At routine test (100% production),
Vini = 1.2 x VIOTM, tini = 1s;
Method b1: Vpd(m) = 1.875 x VIORM, tm = 1s or
Method b2: Vpd(m) = Vini, tm = tini		 ≤ 5
CIO Barrier capacitance, input to output(4) VIO = 0.4 × sin (2πft), f = 1MHz 3.5 pF
RIO Insulation resistance(4) VIO = 500V, TA = 25°C > 1012 Ω
VIO = 500V, 100°C ≤ TA ≤ 125°C > 1011
VIO = 500V, TS = 150°C > 109
Pollution degree 2
Climatic category 55/125/21
UL 1577
VISO(UL) Withstand isolation voltage VTEST = VISO(UL)= 5000 VRMS, t = 60 s (qualification),
VTEST = 1.2 × VISO(UL) = 6000 VRMS, t = 1 s (100% production)		 5000 VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase it.
(2) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(3) Testing is carried out in oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is the electrical discharge caused by a partial discharge (pd).