SLLSFZ6 Data sheet

SLLSFZ6A November 2024 – February 2025 TUSB5461-Q1

PRODUCTION DATA

6.4.4 Linear EQ Configuration

Each of the TUSB5461-Q1 receiver lanes has individual controls for receiver equalization. The receiver equalization gain value can be controlled either through I²C registers or through GPIOs. Table 6-7 details the gain value for each available combination when the TUSB5461-Q1 is in GPIO mode. These same options are also available in I²C mode by updating registers DP0EQ_SEL, DP1EQ_SEL, DP2EQ_SEL, DP3EQ_SEL, EQ1_SEL, EQ2_SEL, and SSEQ_SEL.

Table 6-7 USB Downstream Facing Port Receiver (RX1 and RX2 Pins) Equalization Control

Register(s): EQ1_SEL or EQ2_SEL Equalization Setting #	EQ1 PIN Level	EQ0 PIN Level	EQ Gain at 2.5 GHz minus Gain at 100MHz (dB)
0	0	0	-1.0
1	0	R	0.0
2	0	F	0.9
3	0	1	1.8
4	R	0	2.6
5	R	R	3.4
6	R	F	4.0
7	R	1	4.6
8	F	0	5.2
9	F	R	5.7
10	F	F	6.1
11	F	1	6.5
12	1	0	6.8
13	1	R	7.1
14	1	F	7.5
15	1	1	7.8

Table 6-8 USB Upstream Facing Port Receiver (SSTX Pins) Equalization Control

Register(s): SSEQ_SEL Equalization Setting #	SSEQ1 PIN LEVEL	SSEQ0 PIN LEVEL	EQ Gain at 2.5GHz minus Gain at 100MHz (dB)
0	0	0	-0.5
1	0	R	0.6
2	0	F	1.5
3	0	1	2.5
4	R	0	3.2
5	R	R	4.0
6	R	F	4.6
7	R	1	5.2
8	F	0	5.7
9	F	R	6.3
10	F	F	6.6
11	F	1	7.1
12	1	0	7.4
13	1	R	7.8
14	1	F	8.0
15	1	1	8.4

Table 6-9 DisplayPort Receiver (DP[3:0] Pins) Equalization Control

Register(s): DP0EQ_SEL, DP1EQ_SEL, DP2EQ_SEL, or DP3EQ_SEL Equalization Setting #	DPEQ1 PIN LEVEL	DPEQ0 PIN LEVEL	EQ Gain at 2.7/4.05/5GHz minus Gain at 100MHz (dB)
0	0	0	0.4/0.8/0.83
1	0	R	2.0/3.1/3.4
2	0	F	3.0/4.6/5.0
3	0	1	4.2/6.0/6.5
4	R	0	5.0/7.0/7.5
5	R	R	6.0/8.0/8.4
6	R	F	6.5/8.7/9.1
7	R	1	7.2/9.4/9.8
8	F	0	7.8/10.0/10.3
9	F	R	8.3/10.4/10.7
10	F	F	8.7/10.7/10.9
11	F	1	9.1/11.1/11.2
12	1	0	9.4/11.3/11.3
13	1	R	9.7/11.5/11.5
14	1	F	10.0/11.7/11.6
15	1	1	10.2/11.8/11.7