SLLSFZ6 Data sheet

SLLSFZ6A November 2024 – February 2025 TUSB5461-Q1

PRODUCTION DATA

7.1 TUSB5461-Q1 Registers

Table 7-1 lists the TUSB5461-Q1 registers. All register offset addresses not listed in Table 7-1 should be considered as reserved locations and the register contents should not be modified.

Table 7-1 TUSB5461-Q1 Registers

Offset	Acronym	Register Name	Section
0xA	General_1	General Register	Go
0xB	TXEQ_CTRL	TX EQ Control	Go
0x10	DP01EQ_SEL	DisplayPort Lane 0 and 1 EQ Control	Go
0x11	DP23EQ_SEL	DisplayPort Lane 2 and 3 EQ Control	Go
0x12	DisplayPort_1	AUX Snoop Status	Go
0x13	DisplayPort_2	DP Lane Enable/Disable Control	Go
0x1C	AEQ_CONTROL1	AEQ Controls	Go
0x1D	AEQ_CONTROL2	AEQ Controls	Go
0x1E	AEQ_LONG	AEQ setting for Long channel	Go
0x20	USBC_EQ	EQ control for RX1 and RX2 receivers	Go
0x21	SS_EQ	EQ Control for SSTX receiver	Go
0x22	USB3_MISC	Misc USB3 Controls	Go
0x24	USB_STATUS	USB state machine status	Go
0x32	VOD_CTRL	VOD Linearity and AEQ Controls	Go
0x3B	AEQ_STATUS	Full and Fast AEQ status	Go

Complex bit access types are encoded to fit into small table cells. Table 7-2 shows the codes that are used for access types in this section.

Table 7-2 TUSB5461-Q1 Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
RH	R H	Read Set or cleared by hardware
Write Type
W	W	Write
W1S	W 1S	Write 1 to set
WS	W	Write
Reset or Default Value
-n		Value after reset or the default value

7.1.1 General_1 Register (Offset = 0xA) [reset = 0x1]

General_1 is shown in Table 7-3.

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This register is used to select between USB and DisplayPort modes as well as selecting the orientation of the MUX. Software can set the EQ_OVERRIDE ti use the EQ registers instead of pins.

Table 7-3 General_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	SSRX_LIMIT_ENABLE	R/W	0x0	Limited redriver mode enable for SSRX transmitter. 0x0 = Linear Redriver 0x1 = Limited Redriver
6	RESERVED	R	0x0	Reserved
5	SWAP_HPDIN	R/W	0x0	Controls which pin HPDIN is derived from. 0x0 = HPDIN is in default location 0x1 = HPDIN location is swapped (PIN 15 to PIN 24, or PIN 24 to PIN 15).
4	EQ_OVERRIDE	R/W	0x0	This field allows software to use EQ settings from registers instead of value sampled from pins. 0x0 = EQ settings based on sampled state of EQ pins. 0x1 = EQ settings based on programmed value of each of the EQ registers.
3	HPDIN_OVERRIDE	R/W	0x0	Overrides HPDIN pin state. 0x0 = HPD_IN based on HPD_IN pin. 0x1 = HPD_IN high.
2	FLIP_SEL	R/W	0x0	This field controls the orientation. 0x0 = Normal Orientation 0x1 = Flip orientation.
1-0	CTLSEL	R/W	0x1	Controls the DP and USB modes. 0x0 = Disabled. All RX and TX for USB3 and DisplayPort are disabled. 0x1 = USB3 only enabled. 0x2 = Four Lanes of DisplayPort enabled. 0x3 = USB3 and Two DisplayPort Lanes.

7.1.2 TXEQ_CTRL Register (Offset = 0xB) [reset = 0x6C]

TXEQ_CTRL is shown in Table 7-4.

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This register controls the pre-shoot and de-emphasis levels for SSRX when limited redriver mode is enabled.

Table 7-4 TXEQ_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	TX_PRESHOOT	R/W	0x1	SSRX TX pre-shoot level (pre-cursor). 0x0 = 1.5dB 0x1 = 2dB 0x2 = 2.3dB 0x3 = 2.8dB
5	TX_PRESHOOT_EN	R/W	0x1	SSRX TX pre-shoot (pre-cursor) enabled. Valid only when SSRX_LIMIT_ENABLE = 1. 0x0 = Disabled (0dB) 0x1 = Enabled
4-3	TX_DEEPHASIS	R/W	0x1	SSRX TX de-emphasis level (post-cursor) 0x0 = -1.5dB 0x1 = -2.1dB 0x2 = -3.2dB 0x3 = -3.8dB
2	TX_DEEPHASIS_EN	R/W	0x1	SSRX TX de-emphasis (post-cursor) enable. Valid only when SSRX_LIMIT_ENABLE = 1. 0x0 = Disabled (0dB) 0x1 = Enabled
1-0	RESERVED	R	0x0	Reserved

7.1.3 DP01EQ_SEL Register (Offset = 0x10) [reset = 0x0]

DP01EQ_SEL is shown in Table 7-5.

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This register controls the receiver equalization setting for the DisplayPort receivers 0 and 1.

Table 7-5 DP01EQ_SEL Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	DP1EQ_SEL	RH/W	0x0	Field selects EQ for DP lane 1 pins. When EQ_OVERRIDE = 0b, this field reflects the sampled state of DPEQ[1:0] pins. When EQ_OVERRIDE = 1b, software can change the EQ setting for DP Lane 1 based on value written to this field.
3-0	DP0EQ_SEL	RH/W	0x0	Field selects EQ for DP lane 0 pins. When EQ_OVERRIDE = 0b, this field reflects the sampled state of DPEQ[1:0] pins. When EQ_OVERRIDE = 1b, software can change the EQ setting for DP Lane 0 based on value written to this field.

7.1.4 DP23EQ_SEL Register (Offset = 0x11) [reset = 0x0]

DP23EQ_SEL is shown in Table 7-6.

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This register controls the receiver equalization setting for the DisplayPort receivers 2 and 3.

Table 7-6 DP23EQ_SEL Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	DP3EQ_SEL	RH/W	0x0	Field selects EQ for DP lane 3 pins. When EQ_OVERRIDE = 0b, this field reflects the sampled state of DPEQ[1:0] pins. When EQ_OVERRIDE = 1b, software can change the EQ setting for DP Lane 3 based on value written to this field.
3-0	DP2EQ_SEL	RH/W	0x0	Field selects EQ for DP lane 2 pins. When EQ_OVERRIDE = 0b, this field reflects the sampled state of DPEQ[1:0] pins. When EQ_OVERRIDE = 1b, software can change the EQ setting for DP Lane 2 based on value written to this field.

7.1.5 DisplayPort_1 Register (Offset = 0x12) [reset = 0x0]

DisplayPort_1 is shown in Table 7-7.

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This register provides status of AUX snooping when AUX Snooping is enabled.

Table 7-7 DisplayPort_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0x0	Reserved
6-5	SET_POWER_STATE	RH	0x0	This field represents the snooped value of the AUX write to DPCD address 0x00600. When AUX_SNOOP_DISABLE = 0b, the enable/disable of DP lanes based on the snooped value. When AUX_SNOOP_DISABLE = 1b, then DP lane enable/disable are determined by state of DPx_DISABLE registers, where x = 0, 1, 2, or 3. This field is reset to 0h by hardware when CTLSEL1 changes from a 1b to a 0b.
4-0	LANE_COUNT_SET	RH	0x0	This field represents the snooped value of AUX write to DPCD address 0x00101 register. When AUX_SNOOP_DISABLE = 0b, DP lanes enabled specified by the snoop value. Unused DP lanes are disabled to save power. When AUX_SNOOP_DISABLE = 1b, then DP lanes enable/disable are determined by DPx_DISABLE registers, where x = 0, 1, 2, or 3. This field is reset to 0h by hardware when CTLSEL1 changes from a 1b to a 0b.

7.1.6 DisplayPort_2 Register (Offset = 0x13) [reset = 0x0]

DisplayPort_2 is shown in Table 7-8.

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This register provides controls for enabling and disabling AUX snooping and individual DP lanes.

Table 7-8 DisplayPort_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	AUX_SNOOP_DISABLE	R/W	0x0	Controls whether DP lanes are enabled based on AUX snooped value or registers. 0x0 = AUX snoop enabled. 0x1 = AUX snoop disabled. DP lanes are controlled by registers.
6	RESERVED	R	0x0	Reserved
5-4	AUX_SBU_OVR	R/W	0x0	This field overrides the AUXP/N to SBU1/2 connect and disconnect based on CTL1 and FLIP. Changing this field to 01b or 10b allows traffic to pass through AUX to SBU regardless of the state of CTLSEL1 and FLIPSEL register. 0x0 = AUX to SBU connection determined by CTLSEL1 and FLIPSEL 0x1 = AUXP -> SBU1 and AUXN -> SBU2 0x2 = AUXP -> SBU2 and AUXN -> SBU1 0x3 = AUX to SBU open.
3	DP3_DISABLE	R/W	0x0	When AUX_SNOOP_DISABLE = 1b, this field can be used to enable or disable DP lane 3. When AUX_SNOOP_DISABLE = 0b, changes to this field has no effect on lane 3 functionality. 0x0 = DP Lane 3 enabled. 0x1 = DP Lane 3 disabled.
2	DP2_DISABLE	R/W	0x0	When AUX_SNOOP_DISABLE = 1b, this field can be used to enable or disable DP lane 2. When AUX_SNOOP_DISABLE = 0b, changes to this field has no effect on lane 2 functionality. 0x0 = DP Lane 2 enabled. 0x1 = DP Lane 2 disabled.
1	DP1_DISABLE	R/W	0x0	When AUX_SNOOP_DISABLE = 1b, this field can be used to enable or disable DP lane 1. When AUX_SNOOP_DISABLE = 0b, changes to this field has no effect on lane 1 functionality. 0x0 = DP Lane 1 enabled. 0x1 = DP Lane 1 disabled.
0	DP0_DISABLE	R/W	0x0	When AUX_SNOOP_DISABLE = 1b, this field can be used to enable or disable DP lane 0. When AUX_SNOOP_DISABLE = 0b, changes to this field has no effect on lane 0 functionality. 0x0 = DP Lane 0 enabled. 0x1 = DP Lane 0 disabled.

7.1.7 AEQ_CONTROL1 Register (Offset = 0x1C) [reset = 0x80]

AEQ_CONTROL1 is shown in Table 7-9.

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This register is used to enable adaptive EQ and select between Fast and Full adaptive EQ.

Table 7-9 AEQ_CONTROL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	FULLAEQ_UPPER_EQ	R/W	0x8	Maximum EQ value to check for full AEQ mode
3	USB3_U1_DISABLE	R/W	0x0	This field when set causes entry to U3 instead of U1 when electrical idle is detected. 0x0 = U1 entry after electrical idle. 0x1 = U3 entry after electrical idle.
2-1	AEQ_MODE	R/W	0x0	Selects between Fast and 2 Full Adaption modes 0x0 = Fast AEQ. 0x1 = Full AEQ with hits counted at mideye for every EQ. 0x2 = Fast AEQ. 0x3 = Full AEQ with hits counted at mideye only for EQ equal 0.
0	AEQ_EN	R/W	0x0	Controls whether or not adaptive EQ for USB downstream facing port is enabled. 0x0 = AEQ disabled 0x1 = AEQ enabled

7.1.8 AEQ_CONTROL2 Register (Offset = 0x1D) [reset = 0x10]

AEQ_CONTROL2 is shown in Table 7-10.

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This register allows for controls for the Fast AEQ limits as well as adding or reducing final EQ value used by the Full AEQ function.

Table 7-10 AEQ_CONTROL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	OVER_EQ_SIGN	R/W	0x0	Selects the sign for OVER_EQ_CTRL field. 0x0 = positive 0x1 = negative
6	RESERVED	R	0x0	Reserved
5-3	FASTAEQ_LIMITS	R/W	0x2	Selects the upper/lower limits of DAC for determining short vs long channel. 0x0 = +/- 0mV 0x1 = +/- 40mV 0x2 = +/- 80mV 0x3 = +/- 120mV 0x4 = +/- 160mV 0x5 = +/- 200mV 0x6 = +/- 240mV 0x7 = +/- 280mV
2-0	OVER_EQ_CTRL	R/W	0x0	This field increases or decreases the AEQ by value programmed into this field. For example, full AEQ value is 6 and this field is programmed to 2 and OVER_EQ_SIGN = 0, then EQ value used is 8. This field is only used in Full AEQ mode. 0x0 = 0 or -8 0x1 = 1 or -7 0x2 = 2 or -6 0x3 = 3 or -5 0x4 = 4 or -4 0x5 = 5 or -3 0x6 = 6 or -2 0x7 = 7 or -1

7.1.9 AEQ_LONG Register (Offset = 0x1E) [reset = 0x77]

AEQ_LONG is shown in Table 7-11.

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This register is used to program the EQ used for long channel setting when Fast AEQ is enabled.

Table 7-11 AEQ_LONG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	LONG_EQ2	R/W	0x7	When AEQ_EN = 1 and AEQ_MODE = x0, selects EQ setting for USB downstream facing port1 (RX2) when long channel is detected. Value programmed into this field can provide best Rx JTOL results for long channel configuration.
3-0	LONG_EQ1	R/W	0x7	When AEQ_EN = 1 and AEQ_MODE = x0, selects EQ setting for USB downstream facing port2 (RX1) when long channel is detected. Value programmed into this field can provide best Rx JTOL results for long channel configuration.

7.1.10 USBC_EQ Register (Offset = 0x20) [reset = 0x0]

USBC_EQ is shown in Table 7-12.

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This register controls the receiver equalization setting for the DFP (RX1 and RX2).

Table 7-12 USBC_EQ Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	EQ2_SEL	RH/W	0x0	If AEQ_EN = 0, this field selects EQ for USB3.1 RX2 receiver which faces the USB-C receptacle. When EQ_OVERRIDE = 0b, this field reflects the sampled state of EQ[1:0] pins. When EQ_OVERRIDE = 1b, software can change the EQ setting for RX2p/n pins based on value written to this field. When AEQ_EN = 1 and AEQ_MODE = x0, selects EQ setting for USB downstream facing port1 (RX2) when short channel is detected. Value programmed into this field can provide best Rx JTOL results for short channel configuration.
3-0	EQ1_SEL	RH/W	0x0	If AEQ_EN = 0, this field selects EQ for USB3.1 RX1 receiver which faces the USB-C receptacle. When EQ_OVERRIDE = 0b, this field reflects the sampled state of EQ[1:0] pins. When EQ_OVERRIDE = 1b, software can change the EQ setting for RX1p/n pins based on value written to this field. When AEQ_EN = 1 and AEQ_MODE = x0, selects EQ setting for USB downstream facing port1 (RX1) when short channel is detected. Value programmed into this field can provide best Rx JTOL results for short channel configuration.

7.1.11 SS_EQ Register (Offset = 0x21) [reset = 0x0]

SS_EQ is shown in Table 7-13.

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This register controls the receiver equalization setting for the UFP (SSTX).

Table 7-13 SS_EQ Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0x0	Reserved
3-0	SSEQ_SEL	RH/W	0x0	This field selects EQ for USB3.1 SSTX receiver which faces the USB host. When EQ_OVERRIDE = 0b, this field reflects the sampled state of SSEQ[1:0] pins. When EQ_OVERRIDE = 1b, software can change the EQ setting for SSTXp/n pins based on value written to this field.

7.1.12 USB3_MISC Register (Offset = 0x22) [reset = 0x44]

USB3_MISC is shown in Table 7-14.

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Table 7-14 USB3_MISC Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RXD_START_TERM	R/W	0x0	Termination setting at start of RX detection following warm reset and at entry to SS.Inactive. 0x0 = Maintain termination. Same as tusb1046 0x1 = Turn off termination. Avoid compliance failures due to race between local and remote rxd in case of disconnect. If connection remains next state was polling regardless.
6	LFPS_EQ	R/W	0x1	Controls whether settings of EQ based on EQ1_SEL, EQ2_SEL, and SSEQ_SEL applies to received LFPS signal. 0x0 = EQ set to zero when receiving LFPS 0x1 = EQ set by the related registers when receiving LFPS.
5	U2U3_LFPS_DEBOUNCE	R/W	0x0	Controls whether or not incoming LFPS is debounced or not. 0x0 = No debounce of LFPS before U2/U3 exit. 0x1 = 200us debounce of LFPS before U2/U3 exit.
4	DISABLE_U2U3_RXDET	R/W	0x0	Controls whether or not Rx.Detect is performed in U2/U3 state. 0x0 = Rx.Detect in U2/U3 enabled. 0x1 = Rx.Detect in U2/U3 disabled.
3-2	DFP_RXDET_INTERVAL	R/W	0x1	This field controls the Rx.Detect interval for the downstream facing port (TX1P/N and TX2P/N). 0x0 = Reserved 0x1 = 6ms 0x2 = 36ms 0x3 = 84ms
1	DIS_WARM_RESET_RXD	R/W	0x0	Disables receiver detection following warm reset if device starts polling during warm reset. 0x0 = whether receiver detection is done following warm reset depends on other settings. 0x1 = if USB FSM detects that device started polling during warm reset, receiver detection is not performed.
0	USB_COMPLIANCE_CTRL	R/W	0x0	Controls whether compliance mode detection is determined by FSM or disabled 0x0 = Compliance mode determined by FSM. 0x1 = Compliance mode disabled.

7.1.13 USB_STATUS Register (Offset = 0x24) [reset = 0x41]

USB_STATUS is shown in Table 7-15.

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Table 7-15 USB_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
7	USB_FASTAEQ_STAT	RH	0x0	When AEQ_EN = 1 and AEQ_MODE = x0, this status field indicates whether short or long EQ setting is used. When AEQ_EN = 0, this field defaults to 0h. 0x0 = Short channel EQ used. 0x1 = Long channel EQ used.
6	USB_AEQDONE_STAT	RH	0x1	This field is low while AEQ is active and high when AEQ is done. The bit is valid when U0_STAT and AEQ_EN = 1 or when FORCE_AEQ_EN = 1 and HW has reset FORCE_AEQ back to 0. 0x0 = AEQ is running 0x1 = AEQ is done
5	AEQ_HC_OVERFLOW	RH	0x0	13-bit AEQ hit counter overflow status
4	RESERVED	R	0x0	Reserved
3	CM_ACTIVE	RH	0x0	Compliance mode status. 0x0 = Not in USB3 compliance mode. 0x1 = In USB3 compliance mode.
2	U0_STAT	RH	0x0	U0 Status. Set if the device enters U0 state.
1	U2U3_STAT	RH	0x0	U2/U3 Status. Set if the device enters U2/U3 state.
0	DISC_STAT	RH	0x1	Disconnect Status. Set if the device enters Disconnect state.

7.1.14 VOD_CTRL Register (Offset = 0x32) [reset = 0x40]

VOD_CTRL is shown in Table 7-16.

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This register controls the transmitters output linearity range for both UFP and DFP. When device is configured for limited redriver (SSRX_LIMIT_ENABLE field is set), USB_SSRX_VOD controls the VOD level for SSRX limited driver.

Table 7-16 VOD_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	LFPS_TX12_VOD	R/W	0x1	VOD linearity control for TX1 or TX2 when LFPS is being transmitted. 0x0 = LINR_L3 (highest) 0x1 = LINR_L2 0x2 = LINR_L1 0x3 = LINR_L0 (lowest)
5-4	DP_VOD	R/W	0x0	VOD linearity control for DP paths. 0x0 = LINR_L3 (highest) 0x1 = LINR_L2 0x2 = LINR_L1 0x3 = LINR_L0 (lowest)
3-2	USB_TX12_VOD	R/W	0x0	VOD linearity control for USB downstream facing ports (TX1 and TX2). 0x0 = LINR_L3 (highest) 0x1 = LINR_L2 0x2 = LINR_L1 0x3 = LINR_L0 (lowest)
1-0	USB_SSRX_VOD	R/W	0x0	VOD linearity control for USB upstream facing port (SSRX). When SSRX_LIMIT_ENABLE = 1, then this field controls the limited VOD for SSRX. 0x0 = LINR_L3 (highest) 0x1 = LINR_L2 0x2 = LINR_L1 0x3 = LINR_L0 (lowest)

7.1.15 AEQ_STATUS Register (Offset = 0x3B) [reset = 0x0]

AEQ_STATUS is shown in Table 7-17.

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This register provides the status of AEQ function.

Table 7-17 AEQ_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	RESERVED	R	0x0	Reserved
4	DONE_STAT	RH	0x0	This flag is set after DAC wait timer expires.
3-0	AEQ_STAT	RH	0x0	Optimal EQ determined by FSM after the completion of Full AEQ. This field also indicates the EQ used for Fast AEQ. This field also includes the value programmed into OVER_EQ_CTRL field.