SLLSG20 March   2026 MCF8329HS

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Comm
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Three Phase BLDC Gate Drivers
      2. 7.3.2  Gate Drive Architecture
        1. 7.3.2.1 Dead time and Cross Conduction Prevention
      3. 7.3.3  AVDD Linear Voltage Regulator
      4. 7.3.4  DVDD Voltage Regulator
        1. 7.3.4.1 AVDD Powered VREG
        2. 7.3.4.2 External Supply for VREG
        3. 7.3.4.3 External MOSFET for VREG Supply
      5. 7.3.5  Low-Side Current Sense Amplifier
      6. 7.3.6  Device Interface Modes
        1. 7.3.6.1 Interface - Control and Monitoring
        2. 7.3.6.2 I2C Interface
      7. 7.3.7  Motor Control Input Options
        1. 7.3.7.1 Analog-Mode Motor Control
        2. 7.3.7.2 PWM-Mode Motor Control
        3. 7.3.7.3 Frequency-Mode Motor Control
        4. 7.3.7.4 I2C based Motor Control
        5. 7.3.7.5 Input Control Signal Profiles
          1. 7.3.7.5.1 Linear Control Profiles
          2. 7.3.7.5.2 Staircase Control Profiles
          3. 7.3.7.5.3 Forward-Reverse Profiles
          4. 7.3.7.5.4 Multi-Reference Mode Operation
          5. 7.3.7.5.5 Input Reference Transfer Function without Profiler
      8. 7.3.8  Bootstrap Capacitor Initial Charging
      9. 7.3.9  Starting the Motor Under Different Initial Conditions
        1. 7.3.9.1 Case 1 – Motor is Stationary
        2. 7.3.9.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 7.3.9.3 Case 3 – Motor is Spinning in the Reverse Direction
      10. 7.3.10 Motor Start Sequence (MSS)
        1. 7.3.10.1 Initial Speed Detect (ISD)
        2. 7.3.10.2 Motor Resynchronization
        3. 7.3.10.3 Reverse Drive
          1. 7.3.10.3.1 Reverse Drive Tuning
        4. 7.3.10.4 Motor Start-up
          1. 7.3.10.4.1 Align
          2. 7.3.10.4.2 Double Align
          3. 7.3.10.4.3 Initial Position Detection (IPD)
            1. 7.3.10.4.3.1 IPD Operation
            2. 7.3.10.4.3.2 IPD Release
            3. 7.3.10.4.3.3 IPD Advance Angle
          4. 7.3.10.4.4 Slow First Cycle Startup
          5. 7.3.10.4.5 Open Loop
          6. 7.3.10.4.6 Transition from Open to Closed Loop
      11. 7.3.11 Closed Loop Operation
        1. 7.3.11.1 Closed loop accelerate
        2. 7.3.11.2 Speed PI Control
        3. 7.3.11.3 Current PI Control
        4. 7.3.11.4 Overmodulation
        5. 7.3.11.5 Power Loop
        6. 7.3.11.6 Modulation Index Control
        7. 7.3.11.7 Motor Speed Limit
        8. 7.3.11.8 Input DC Power Limit
      12. 7.3.12 Maximum Torque Per Ampere (MTPA) Control
      13. 7.3.13 Flux Weakening Control
      14. 7.3.14 Motor Parameters
        1. 7.3.14.1 Motor Resistance
        2. 7.3.14.2 Motor Inductance
        3. 7.3.14.3 Motor Back-EMF constant
      15. 7.3.15 Motor Parameter Extraction Tool (MPET)
      16. 7.3.16 Single Hall Sensor Operation
      17. 7.3.17 Anti-Voltage Surge (AVS)
      18. 7.3.18 Active Braking
      19. 7.3.19 Output PWM Switching Frequency
      20. 7.3.20 PWM Dithering
      21. 7.3.21 Voltage Sense Scaling
      22. 7.3.22 Motor Stop Options
        1. 7.3.22.1 Coast (Hi-Z) Mode
        2. 7.3.22.2 Low-Side Braking
        3. 7.3.22.3 Active Spin-Down
      23. 7.3.23 FG Configuration
        1. 7.3.23.1 FG Output Frequency
        2. 7.3.23.2 FG in Open-Loop
        3. 7.3.23.3 FG During Motor Stop
        4. 7.3.23.4 FG Behavior During Fault
      24. 7.3.24 Protections
        1. 7.3.24.1  PVDD Supply Undervoltage Lockout (PVDD_UV)
        2. 7.3.24.2  AVDD Power on Reset (AVDD_POR)
        3. 7.3.24.3  GVDD Undervoltage Lockout (GVDD_UV)
        4. 7.3.24.4  BST Undervoltage Lockout (BST_UV)
        5. 7.3.24.5  MOSFET VDS Overcurrent Protection (VDS_OCP)
        6. 7.3.24.6  VSENSE Overcurrent Protection (SEN_OCP)
        7. 7.3.24.7  Thermal Shutdown (OTSD)
        8. 7.3.24.8  Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)
          1. 7.3.24.8.1 HW_LOCK_ILIMIT Latched Shutdown (HW_LOCK_ILIMIT_MODE = 00xb or 010b)
          2. 7.3.24.8.2 HW_LOCK_ILIMIT Automatic recovery (HW_LOCK_ILIMIT_MODE = 011b or 10xb)
          3. 7.3.24.8.3 HW_LOCK_ILIMIT Report Only (HW_LOCK_ILIMIT_MODE = 110b)
          4. 7.3.24.8.4 HW_LOCK_ILIMIT Disabled (HW_LOCK_ILIMIT_MODE = 111b)
        9. 7.3.24.9  Lock Detection Current Limit (LOCK_ILIMIT)
          1. 7.3.24.9.1 LOCK_ILIMIT Latched Shutdown (LOCK_ILIMIT_MODE = 00xb or 010b)
          2. 7.3.24.9.2 LOCK_ILIMIT Automatic Recovery (LOCK_ILIMIT_MODE = 011b or 10xb)
          3. 7.3.24.9.3 LOCK_ILIMIT Report Only (LOCK_ILIMIT_MODE = 110b)
          4. 7.3.24.9.4 LOCK_ILIMIT Disabled (LOCK_ILIMIT_MODE = 111b)
        10. 7.3.24.10 Motor Lock (MTR_LCK)
          1. 7.3.24.10.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xb or 010b)
          2. 7.3.24.10.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE = 011b or 10xb)
          3. 7.3.24.10.3 MTR_LCK Report Only (MTR_LCK_MODE = 110b)
          4. 7.3.24.10.4 MTR_LCK Disabled (MTR_LCK_MODE = 111b)
        11. 7.3.24.11 Motor Lock Detection
          1. 7.3.24.11.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 7.3.24.11.2 Lock 2: Abnormal BEMF (ABN_BEMF)
          3. 7.3.24.11.3 Lock3: No-Motor Fault (NO_MTR)
        12. 7.3.24.12 EEPROM Fault
        13. 7.3.24.13 I2C CRC Fault
        14. 7.3.24.14 Maximum PVDD (Overvoltage) Protection
        15. 7.3.24.15 Minimum PVDD (Undervoltage) Protection
        16. 7.3.24.16 MPET Faults
        17. 7.3.24.17 Dry Run Detection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Standby Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT)
    5. 7.5 External Interface
      1. 7.5.1 DRVOFF - Gate Driver Shutdown Functionality
      2. 7.5.2 DAC outputs
      3. 7.5.3 Current Sense Amplifier Output
      4. 7.5.4 Oscillator Source
        1. 7.5.4.1 Clock (Internal Oscillator) Frequency
        2. 7.5.4.2 External Clock Source
      5. 7.5.5 External Watchdog
    6. 7.6 EEPROM access and I2C interface
      1. 7.6.1 EEPROM Access
        1. 7.6.1.1 EEPROM Write
        2. 7.6.1.2 EEPROM Read
        3. 7.6.1.3 EEPROM Security
      2. 7.6.2 I2C Serial Interface
        1. 7.6.2.1 I2C Data Word
        2. 7.6.2.2 I2C Write Transaction
        3. 7.6.2.3 I2C Read Transaction
        4. 7.6.2.4 Examples of I2C Communication Protocol Packets
        5. 7.6.2.5 I2C Clock Stretching
        6. 7.6.2.6 CRC Byte Calculation
  9. 8 EEPROM (Non-Volatile) Register Map
    1. 8.1 Algorithm_Configuration Registers
    2. 8.2 Fault_Configuration Registers
    3. 8.3 Hardware_Configuration Registers
    4. 8.4 Internal_Algorithm_Configuration Registers
  10. 9 RAM (Volatile) Register Map
    1. 9.1 Fault_Status Registers
    2. 9.2 System_Status Registers
    3. 9.3 Algorithm_Control Registers
    4. 9.4 Device_Control Registers
    5. 9.5 Algorithm_Variables Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1.      Detailed Design Procedure
      2.      Bootstrap Capacitor and GVDD Capacitor Selection
      3. 10.2.1 Selection of External MOSFET for VREG Power Supply
      4.      Gate Drive Current
      5.      Gate Resistor Selection
      6.      System Considerations in High Power Designs
      7.      Capacitor Voltage Ratings
      8.      External Power Stage Components
    3. 10.3 UL Recognized Component: MCF8329HSULIREER
      1. 10.3.1 IEC 60730 Functional Safety System (applicable for MCF8329HSULIREER only)
      2. 10.3.2 IEC 60730 Self Test Library (available only in MCF8329HSULIREER)
    4. 10.4 Power Supply Recommendations
      1. 10.4.1 Bulk Capacitance
    5. 10.5 Layout
      1. 10.5.1 Layout Guidelines
      2. 10.5.2 Layout Example
      3. 10.5.3 Thermal Considerations
        1. 10.5.3.1 Power Dissipation
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  13. 12Revision History

7.3.24.17 Dry Run Detection

MCF8329HS provides the option of dry run detection when pumps are operating with insufficient fluid. Dry run is a dangerous operating condition that can damage pumps - timely detection and preventive action is necessary to protect pumps. Dry run is characterized by the motor operating continuously at a lower current/power than when operating with sufficient fluid. Dry run detection is enabled when DRY_RUN_MODE ≠ 00b. The threshold speed for dry run detection is configured by DRY_RUN_SPEED_THR - even when enabled, dry run detection is active only when motor speed is higher than DRY_RUN_SPEED_THR. The q-axis current threshold (IDRY_RUN) for detecting dry run can either be fixed across motor speed (DRY_RUN_ILIM_MODE = 0b) or variable (DRY_RUN_ILIM_MODE = 1b). IDRY_RUN is fixed to DRY_RUN_ILIM when DRY_RUN_ILIM_MODE = 0b. When DRY_RUN_ILIM_MODE = 1b, IDRY_RUN varies with motor speed as shown in Figure 7-51. The Iq current must be lower than IDRY_RUN for a deglitch time interval set by DRY_RUN_TDEG before dry run fault is triggered as shown in Figure 7-50 .

MCF8329HS Dry Run Detection Figure 7-50 Dry Run Detection

On detection of dry run condition, action is taken based on DRY_RUN_MODE. If DRY_RUN_MODE is set to 11b, all external FETs are turned off (PWMs are pulled low), nFAULT is pulled low, CONTROLLER_FAULT, DRY_RUN bits are set to 1b until a clear fault command is issued by external MCU through the CLR_FLT bit. If DRY_RUN_MODE is set to 10b, all external FETs are turned off (PWMs are pulled low), nFAULT is pulled low - normal operation resumes automatically (gate driver operation and the nFAULT pin is released) after the tLCK_RETRY (configured by LCK_RETRY) time lapses. The CONTROLLER_FAULT and DRY_RUN bits are reset to 0b after the tLCK_RETRY period expires.

MCF8329HS provides the option to vary IDRY_RUN as a function of motor speed to detect dry run in pumps that can operate at multiple speeds (or flow rates) during normal operation. User must set DRY_RUN_ILIM to the expected Iq current at 100% speed and DRY_RUN_ILIM_FIFTY_PERCENT_SPEED to the expected Iq current at 50% speed. MCF8329HS uses DRY_RUN_ILIM as IDRY_RUN when motor is at 100% speed and DRY_RUN_ILIM_FIFTY_PERCENT_SPEED as IDRY_RUN when motor is at 50% speed. When motor is operating at other speeds, MCF8329HS extrapolates IDRY_RUN as shown in Figure 7-51.

Note: TI recommends subtracting 5-10% from expected Iq current for setting DRY_RUN_ILIM and DRY_RUN_ILIM_FIFTY_PERCENT_SPEED to avoid false dry run faults (due to IDRY_RUN being set too high).
MCF8329HS Variable current threshold (IDRY_RUN) for dry run detection Figure 7-51 Variable current threshold (IDRY_RUN) for dry run detection