SLLU386 August   2024 TIOL221

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 Power Requirements
    2. 2.2 Current Limit Configuration
    3. 2.3 Setup
    4. 2.4 Header Information
    5. 2.5 Jumper Information
    6. 2.6 IO-Link Interface
    7. 2.7 Test Points
    8. 2.8 I2C EEPROM
  8. 3Software
  9. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layouts
    3. 4.3 Bill of Materials (BOM)
  10. 5Additional Information
    1. 5.1 Trademarks

2.1 Power Requirements

L+_24V is the primary supply voltage for the board and must be applied to pin 1 (L+_24V) and pin 3 (GND) of the M12 connector (J2), pin 2 (L+_24V) and pin 3 (GND) of the wire terminal (J1), or test points TP11 (L+_24V) and TP12 (GND).

External Power Supply or Power Accessory Requirements:

  • Nom output voltage: 24VDC
  • Max output current: 1A
  • Efficiency level: V
Note:

TI recommends using an external power supply or power accessory which complies with applicable regional safety standards such as (by example) UL, CSA, VDE, CCC, PE, and so on.

The TIOL221 has an integrated linear voltage regulator (LDO) which can supply power to external components with up to 20mA of current. The LDO can use either the L+_24V as the input voltage or an external 5V supply voltage can be applied to the V5IN pin to reduce the power dissipation in the device.

Table 2-1 Power Supply Specifications
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
V(LP) 24V Input supply voltage 7 24 36 V
V(V5IN) 5V Input supply voltage 4.5 5 5.5 V
V(VOUT) Voltage regulator output VOUT set to 5V 4.75 5 5.25 V
VOUT set to 3.3V 3.13 3.3 3.46 V
I(VOUT) LDO output current 20 mA
V(I) Logic level input voltage at TX1, TX2, EN1, EN2,CS/PP, SDI/NPN, SCK, SPI/PIN 3.3V configuration 3 3.3 3.6 V
5V configuration 4.5 5 5.25 V

The LDO output level is configurable via the VSEL pin. When VSEL is connected to GND, VOUT is configured to provide a 3.3V output with L+_24V as the input supply. When VSEL is left floating, VOUT provides a 3.3V output, with V5IN as the supply input to reduce the power dissipation in the device. When the VSEL is connected to VOUT, VOUT is set to 5V. The VSEL pin status is detected at power-up and the VOUT output level is determined and latched until the next power-up cycle.

Table 2-2 LDO Voltage Selection
VSEL Pin Connection on J17 VOUT

Connected to GND through Pull Down (PD) resistor

3.3V (supplied from L+_24V)

Floating

3.3V (supplied from V5IN)

Connected to VOUT through Pull Up (PU) resistor

5V

An external 5V supply voltage can be applied to TIOL221 V5IN pin by placing a jumper shunt on J13 to connect the device V5IN pin to the boards 5V rail. The 5V net can be supplied by either an external 5V power supply, or from the 5V_LP source when the EVM is mated to a TI Microcontroller board.

An external 5V supply can be connected through either the 5V_EXT and GND pins J7, or TP20 and TP10. A jumper shunt needs to be connected between the 5V_EXT and 5V pins of J5 to connect the 5V_EXT supply the 5V net of the board.

The 5V_LP supply from a TI Microcontroller board is available on pin 21 of J10, or TP22. A jumper shunt needs to be connected between the 5V_LP and 5V pins of J5 to connect the 5V_LP supply to the 5V net of the board.

Test point TP23 can be used to monitor the board 5V net.