SLOA349 March   2025 TAS6584-Q1 , TAS6684-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2SDOUT Configuration
    1. 2.1 SDOUT – I2S Configuration
    2. 2.2 SDOUT – TDM Configuration
  6. 3SDOUT Connection in Multi-Device System
  7. 4Output Current and Voltage Calculation
  8. 5Summary
  9. 6References

2.2 SDOUT – TDM Configuration

The recommendation is to transmit data through the SDOUT1 pin in TDM mode. Bits [7:4] of register 0x25 determine which SDOUT pin can transmit the desired data. Register 0x31 is used to enable output current and voltage predict transmitted on SDOUT pin. The recommendation is to place the 4 channels outputs of one TAS6584-Q1 device in consecutive slots. If the input data has a bit offset set SDOUT to the same offset to avoid overlapping data, this is configured using the 10-bit offset in registers 0x2C, 0x2D, 0x2E and 0x2F. When multiple data groups (Isense, Vpredict, Aux) are enabled at the same time on designated slots, the configuration of the offset is mandatory. The offset is defined as the number of SCLK cycles from the start (MSB) of the audio frame to the start of the data group. Figure 2-2 is typical timing diagram for SDOUT in TDM configuration with bit offsets.

Timing Diagram for SDOUT in TDM Configuration Figure 2-2 Timing Diagram for SDOUT in TDM Configuration

Table 2-8 and Figure 2-3 are SDOUT configuration and timing diagram example of one TAS6584-Q1 device in TDM8 mode without one bit shift offset. Isense of Ch1 to 4 data is placed on slots 1 to 4, and Vpredict of Ch1 to 4 data is placed on slots 5 to 8.

Table 2-8 SDOUT – TDM8 Configuration Example
Register 0x25, bit[7:4] Register 0x31, bit[3:0] Register 0x2C Register 0x2D Register 0x2E Register 0x2F Pin Slot 1-4 Slot 5-8
0000 0011 0x0F 0x80 0x00 0xFF SDOUT1 Isense Ch1-4 Vpredict Ch1-4
Timing Diagram Example for SDOUT in TDM8 Configuration Figure 2-3 Timing Diagram Example for SDOUT in TDM8 Configuration

This is PPC3 script of above TDM8 configuration example.

w c0 25 0F           # TDM mode and 32 bit length for Vpredict and Isense
w c0 26 32           # 32 bit length for Aux
w c0 31 03           # enable Ch1/2/3/4 Vpredict and Isense output.
w c0 2C 0F           # MSB offset of Vpredict, Isense and Aux
w c0 2D 80           # Vpredict LSB offset: 128 bits, slot 5-8
w c0 2E 00           # Isense LSB offset: 0 bit, slot 1-4
w c0 2F FF           # Aux1 LSB, work with 0x2C register to remove Aux1 out of 8 slots
w c0 30 FF           # Aux2 LSB, work with 0x2C register to remove Aux2 out of 8 slots

The maximum SCLK frequency of serial audio port which TAS6x84-Q1 can support is 24.576MHz. The higher the clock frequency, the signal timing design can be more stringent. In the 24.576MHz SCLK clock frequency application, SCLK must be configured to inverted mode to make sure timing stability, and DVDD power must be only supplied to 3.3V. The invert mode configuration register address is 0x20, Table 2-9.

Table 2-9 Register 0x20 Register Descriptions
Bit Field Type Reset Description
7-6 RESERVED R/W 0x0 Reserved
5 BCK_INV_TX R/W 0x0

BCK Polarity of TX

This bit is to set the SDOUT sent at the rising edge of BCK.

This bit sets the inverted BCK mode. In inverted BCK mode, the DAC assumes that the SDOUT edges are aligned to the rising edge of the BCK. Normally it's assumed to be aligned to the falling edge of the BCK.

0: Normal BCK mode

1: Inverted BCK mode
4 BCK_INV_RX R/W 0x0

BCK Polarity of RX

This bit sets the inverted BCK mode. In inverted BCK mode, the

DAC assumes that the LRCK and DIN edges are aligned to the rising edge of the BCK. Normally LRCK and DIN edges are assumed to be aligned to the falling edge of the BCK.

0: Normal BCK mode

1: Inverted BCK mode
3-0 RESERVED R/W 0x0 Reserved

If SCLK frequency is 24.576MHz (96kHz sample rate in TDM8 mode), the PPC3 script of Table 2-8 TDM8 configuration example must add register 0x20 configuration. Because Vpredict data is only available at 48kHz sampling frequency and not supported at 96kHz or 192kHz, so below script only enables current output.

w c0 20 20           # configure SCLK to TX inverted mode 
w c0 25 0F           # TDM mode and 32 bit length for Vpredict and Isense
w c0 26 32           # 32 bit length for Aux
w c0 31 03           # enable Ch1/2/3/4 Vpredict and Isense output.
w c0 2C CF           # MSB offset of Vpredict, Isense and Aux
w c0 2D FF           # Vpredict LSB, work with 0x2C register to remove Vpredict out of 8 slots
w c0 2E 00           # Isense LSB offset: 0 bit, slot 1-4
w c0 2F FF           # Aux1 LSB, work with 0x2C register to remove Aux1 out of 8 slots
w c0 30 FF           # Aux2 LSB, work with 0x2C register to remove Aux2 out of 8 slots