SLOA349 March 2025 TAS6584-Q1 , TAS6684-Q1

2 SDOUT Configuration

The SDOUT requires the serial audio port to operate in I²S or TDM mode data formats. Left-justified and DSP mode formats are not supported. The audio input serial clock (SCLK) and audio frame clock (FSYNC) are reused, and the outgoing data on SDOUT has the same sampling frequency and maximum audio frame size as the audio input signal. The output format follows the audio input format. The data output configuration is mainly controlled by registers 0x25 and 0x31. If output data has a bit offset as SDIN, configure the optional 10-bit offset in registers 0x2C, 0x2D, 0x2E and 0x2F to avoid overlapping data.

Table 2-1 shows the registers tables for SDOUT with descriptions:

Table 2-1 Register 0x25 Register Descriptions

Bit	Field	Type	Reset	Description
7-4	SDOUT selection	R/W	0x1	These bits control the SDOUT output place on SDOUT1 line or SDOUT2 line. These bits are used in conjunction with reg_tx_sel and reg_i2s_chsel Non-TDM mode 0001: For output channel 1/2 in SDOUT1 line and channel 3/4 in SDOUT2 line; (reg_tx_sel=4'b0011) 0010: For output channel 3/4 in SDOUT1 line and channel 1/2 in SDOUT2 line; (reg_tx_sel=4'b0011) TDM Mode 0000: SDOUT1 output Isense and Vpredict and Aux
3-2	I2S Word Length	R/W	0x2	I²S Word Length These bits control output audio interface sample word lengths for channel 1/2 output in non-TDM mode and vpredict output channels in TDM mode. 00: 16 bits 01: 20 bits 10: 24 bits 11: 32 bits
1-0	I2S Word Length	R/W	0x2	I²S Word Length These bits control output audio interface sample word lengths for channel 3/4 output in non-TDM mode and isense output channels in TDM mode. 00: 16 bits 01: 20 bits 10: 24 bits 11: 32 bits

Bit

Field

Type

Reset

Description

7-4

SDOUT selection

R/W

0x1

These bits control the SDOUT output place on SDOUT1 line or

SDOUT2 line.

These bits are used in conjunction with reg_tx_sel and reg_i2s_chsel

Non-TDM mode

0001: For output channel 1/2 in SDOUT1 line and channel 3/4 in

SDOUT2 line; (reg_tx_sel=4'b0011)

0010: For output channel 3/4 in SDOUT1 line and channel 1/2 in

SDOUT2 line; (reg_tx_sel=4'b0011)

TDM Mode

0000: SDOUT1 output Isense and Vpredict and Aux

3-2

I2S Word Length

R/W

0x2

I²S Word Length

These bits control output audio interface sample word lengths for

channel 1/2 output in non-TDM mode and vpredict output channels

in TDM mode.

00: 16 bits

01: 20 bits

10: 24 bits

11: 32 bits

1-0

I2S Word Length

R/W

0x2

I²S Word Length

These bits control output audio interface sample word lengths for

channel 3/4 output in non-TDM mode and isense output channels in

TDM mode.

00: 16 bits

01: 20 bits

10: 24 bits

11: 32 bits

Table 2-2 Register 0x31 Register Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R/W	0x0
5-4	reg_i2s_chsel	R/W	0x0	Select output which channel group in non-TDM mode for SDOUT output, need to set reg_i2s_shift5/6 and reg_word_length5/6 to corresponding channel's shift and length. 00: vpredict ch1/2/3/4; 01: isense ch1/2/3/4; 10: auxiliary channels group1(aux 1/2/3/4);
3-0	reg_tx_sel	R/W	0x0	Enable or disable the output data channel 0000: Disable all the output data channels xxx1: Enable Vpredict Ch1/2/3/4 output xx1x: Enable Isense Ch1/2/3/4 output x1xx: Enable Aux Ch1/2/3/4 output In non-TDM mode, if user needs to output 4 channels, 4'b0011 needs to be set

Bit

Field

Type

Reset

Description

7-6

RESERVED

R/W

0x0

5-4

reg_i2s_chsel

R/W

0x0

Select output which channel group in non-TDM mode for SDOUT

output, need to set reg_i2s_shift5/6 and reg_word_length5/6 to

corresponding channel's shift and length.

00: vpredict ch1/2/3/4;

01: isense ch1/2/3/4;

10: auxiliary channels group1(aux 1/2/3/4);

3-0

reg_tx_sel

R/W

0x0

Enable or disable the output data channel

0000: Disable all the output data channels

xxx1: Enable Vpredict Ch1/2/3/4 output

xx1x: Enable Isense Ch1/2/3/4 output

x1xx: Enable Aux Ch1/2/3/4 output

In non-TDM mode, if user needs to output 4 channels, 4'b0011 needs to be set

Table 2-3 Register 0x2C Register Descriptions

Bit	Field	Type	Reset	Description
7-6	reg_Vpredict _shift5_msb	R/W	0x3	Vpredict shift offset MSB, work with register 0x2D(LSB)
5-4	reg_Isense_ shift6_msb	R/W	0x0	Isense shift offset MSB, work with register 0x2E(LSB)
3-2	reg_Aux_ shift7_msb	R/W	0x3	Aux shift offset MSB, work with register 0x2F(LSB)
1-0	RESERVED	R/W	0x3	Reserved

Table 2-4 Register 0x2D Register Descriptions

Bit	Field	Type	Reset	Description
7-0	reg_Vpredict _shift5_lsb	R/W	0xFF	Vpredict shift offset LSB, work with register 0x2C(MSB) These bits control the offset of audio data in the audio frame for output. The offset is defined as the number of BCK from the starting (MSB) of audio frame to the starting of the desired audio. reg_ Vpredict_shift5 = {reg_Vpredict_shift5_msb, reg_Vpredict_shift5_lsb}; reg_ Vpredict_shift5 controls the offset in Vpredict ch1/2/3/4 path. 0000000000: offset = 0 BCK (no offset) 0000000001: offset = 1 BCK 0000000010: offset = 2 BCKs ... 1111111111: offset = 1023 BCKs

Bit

Field

Type

Reset

Description

7-0

reg_Vpredict _shift5_lsb

R/W

0xFF

Vpredict shift offset LSB, work with register 0x2C(MSB)

These bits control the offset of audio data in the audio frame for

output. The offset is defined as the number of BCK from the starting (MSB) of audio frame to the starting of the desired audio.

reg_ Vpredict_shift5 = {reg_Vpredict_shift5_msb, reg_Vpredict_shift5_lsb};

reg_ Vpredict_shift5 controls the offset in Vpredict ch1/2/3/4 path.

0000000000: offset = 0 BCK (no offset)

0000000001: offset = 1 BCK

0000000010: offset = 2 BCKs

...

1111111111: offset = 1023 BCKs

Table 2-5 Register 0x2E Register Descriptions

Bit	Field	Type	Reset	Description
7-0	reg_Isense _shift6_lsb	R/W	0xFF	Isense shift offset LSB, work with register 0x2C(MSB) These bits control the offset of audio data in the audio frame for output. The offset is defined as the number of BCK from the starting (MSB) of audio frame to the starting of the desired audio. reg_Isense_shift6 = {reg_Isense_shift6_msb, reg_Isense_shift6_lsb}; reg_Isense_shift6 controls the offset in Isense ch1/2/3/4 path. 0000000000: offset = 0 BCK (no offset) 0000000001: offset = 1 BCK 0000000010: offset = 2 BCKs ... 1111111111: offset = 1023 BCKs

Bit

Field

Type

Reset

Description

7-0

reg_Isense _shift6_lsb

R/W

0xFF

Isense shift offset LSB, work with register 0x2C(MSB)

These bits control the offset of audio data in the audio frame for

output. The offset is defined as the number of BCK from the starting (MSB) of audio frame to the starting of the desired audio.

reg_Isense_shift6 = {reg_Isense_shift6_msb, reg_Isense_shift6_lsb};

reg_Isense_shift6 controls the offset in Isense ch1/2/3/4 path.

0000000000: offset = 0 BCK (no offset)

0000000001: offset = 1 BCK

0000000010: offset = 2 BCKs

...

1111111111: offset = 1023 BCKs

Table 2-6 Register 0x2F Register Descriptions

Bit	Field	Type	Reset	Description
7-0	reg_Aux _shift7_lsb	R/W	0xFF	Aux shift offset LSB, work with register 0x2C(MSB) These bits control the offset of audio data in the audio frame for output. The offset is defined as the number of BCK from the starting (MSB) of audio frame to the starting of the desired audio. reg_ Aux_shift7 = {reg_ Aux_shift7_msb, reg_ Aux_shift7_lsb}; reg_ Aux_shift7 controls the offset in Aux ch1/2/3/4 path. 0000000000: offset = 0 BCK (no offset) 0000000001: offset = 1 BCK 0000000010: offset = 2 BCKs ... 1111111111: offset = 1023 BCKs

Bit

Field

Type

Reset

Description

7-0

reg_Aux _shift7_lsb

R/W

0xFF

Aux shift offset LSB, work with register 0x2C(MSB)

These bits control the offset of audio data in the audio frame for

output. The offset is defined as the number of BCK from the starting (MSB) of audio frame to the starting of the desired audio.

reg_ Aux_shift7 = {reg_ Aux_shift7_msb, reg_ Aux_shift7_lsb};

reg_ Aux_shift7 controls the offset in Aux ch1/2/3/4 path.

0000000000: offset = 0 BCK (no offset)

0000000001: offset = 1 BCK

0000000010: offset = 2 BCKs

...

1111111111: offset = 1023 BCKs