SLOSED5 December   2024 TRF1213

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Fully-Differential Amplifier
      2. 6.3.2 Single Supply Operation
    4. 6.4 Device Functional Modes
      1. 6.4.1 Power-Down Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Driving a High-Speed ADC
      2. 7.1.2 Calculating Output Voltage Swing
      3. 7.1.3 Thermal Considerations
    2. 7.2 Typical Applications
      1. 7.2.1 TRF1213 in Receive Chain
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

at TA = 25°C, VDD = 5V, 50Ω single-ended input, and 100Ω differential output (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AC PERFORMANCE
Sds21 Power gain f = 0.5GHz 13.8 dB
f = 2GHz 14
f = 4GHz 14
f = 8GHz 13.8
f = 10GHz 14.5
f = 12GHz 15.2
Sss11 Input return loss f = 10MHz to 12GHz –12 dB
Ssd12 Reverse isolation f = 10GHz –34 dB
ImbGAIN Gain imbalance f = 10MHz to 12GHz ±0.3 dB
ImbPHASE Phase imbalance f = 10MHz to 12GHz ±3 degrees
CMRR Common-mode rejection ratio(1) f = 10GHz –32 dB
HD2 Second-order harmonic distortion PO = 3dBm f = 0.5GHz –72 dBc
f = 2GHz –59
f = 4GHz –56
f = 6GHz –47
HD3 Third-order harmonic distortion PO = 3dBm f = 0.5GHz –76 dBc
f = 2GHz –64
f = 4GHz –55
IMD2 Second-order intermodulation distortion PO = –5dBm per tone,
10MHz spacing		 f = 0.5GHz –72 dBc
f = 2GHz –61
f = 4GHz –58
f = 8GHz –53
f = 10GHz –68
f = 12GHz –69
IMD3 Third-order intermodulation distortion PO = –5dBm per tone,
10MHz spacing		 f = 0.5GHz –92 dBc
f = 2GHz –82
f = 4GHz –78
f = 8GHz –74
f = 10GHz –72
f = 12GHz –67
OP1dB Output 1dB compression point f = 0.5GHz 12.7 dBm
f = 2GHz 13.3
f = 4GHz 14.4
f = 8GHz 15.2
f = 10GHz 14.6
f = 12GHz 14.8
OIP2 Output second-order intercept point PO = –5dBm per tone,
10MHz spacing		 f = 0.5GHz 67 dBm
f = 2GHz 56
f = 4GHz 53
f = 8GHz 48
f = 10GHz 63
f = 12GHz 64
OIP3 Output third-order intercept point PO = –5dBm per tone,
10MHz spacing		 f = 0.5GHz 41 dBm
f = 2GHz 36
f = 4GHz 34
f = 8GHz 32
f = 10GHz 31
f = 12GHz 28.5
NF Noise figure f = 0.5GHz 7.9 dB
f = 2GHz 8.2
f = 4GHz 8.6
f = 8GHz 10.8
f = 10GHz 11.8
f = 12GHz 12
IMPEDANCE
ZO-DIFF Differential output impedance f = dc (internal to the device) 12 Ω
RINM Internal INM resistance 50 Ω
CINM Internal INM capacitance 12 pF
POWER SUPPLY
IQA Active current Current on VDD pin, PD = 0 174 mA
IQPD Power-down quiescent current Current on VDD pin, PD = 1 11 mA
ENABLE
VPDHIGH PD pin logic high 1.45 V
VPDLOW PD pin logic low 0.8 V
IPDBIAS PD bias current (current on PD pin) PD = high (1.8V logic) 40 100 µA
PD = high (3.3V logic) 200 250
CPD PD pin capacitance 2 pF
(1) Calculated using the formula (S21 – S31) / (S21 + S31). Port-1: INP, Port-2: OUTP, Port-3: OUTM.