SLPS764B September   2024  – December 2025 RES60A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Absolute and Ratiometric Tolerances
      2. 6.3.2 Ultra-Low Noise
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Battery Stack Measurement
      2. 7.1.2 Gain Scaling the RES60A-Q1 With the RES11A-Q1
      3. 7.1.3 HIPOT and OVST
        1. 7.1.3.1 Mechanisms of HIPOT
        2. 7.1.3.2 Extended Validation of HIPOT
      4. 7.1.4 Hot Swap Response
      5. 7.1.5 High-frequency Response
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 PSpice® for TI
        2. 8.1.1.2 TINA-TI™ Simulation Software (Free Download)
        3. 8.1.1.3 TI Reference Designs
        4. 8.1.1.4 Analog Filter Designer
        5. 8.1.1.5 RES60A-Q1 Ratio and Voltage Error Calculator
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

3 Description

The RES60A-Q1 is a matched resistive divider, implemented in thin-film SiCr with Texas Instruments' modern, high-performance, analog wafer process. A high quality SiO2 insulative layer encapsulates the resistors and enables usage at extremely high voltages, up to 1400VDC for sustained operation or 4000VDC for HiPOT testing (60s). The device has a nominal input resistance of RHV = 12.5MΩ, and is available in several nominal ratios to meet a wide array of system needs.

The RES60A-Q1 series features high ratio matching precision, with the measured ratio of each divider within ±0.1% (max) of the nominal. This precision is maintained over the specified temperature range and aging, with a cumulative drift of only ±0.2% (max). Therefore, the lifetime tolerance of an uncalibrated RES60A-Q1 remains within a ±0.3% (max) envelope.

The RES60A-Q1 is automotive qualified under AEC-Q200 temperature grade 1, with a specified temperature range from –40°C to +125°C. The device is offered in an 8-pin SOIC package, with nominal body size 7.5mm × 5.85mm, and features creepage and clearance distances of at least 8.5mm between the high-voltage and low-voltage pins.

Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2)
RES60A-Q1 DWV (SOIC, 8) 5.85mm × 11.5mm
(1) For more information, see Section 10.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
Device Information
PART NUMBER NOMINAL RATIO

(RHV:RLV)
RES60A145-Q1 145:1
RES60A210-Q1 210:1
RES60A315-Q1 315:1
RES60A410-Q1 410:1
RES60A500-Q1 500:1
RES60A610-Q1 610:1
RES60A100-Q1 1000:1