SLPS764B September   2024  – December 2025 RES60A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Absolute and Ratiometric Tolerances
      2. 6.3.2 Ultra-Low Noise
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Battery Stack Measurement
      2. 7.1.2 Gain Scaling the RES60A-Q1 With the RES11A-Q1
      3. 7.1.3 HIPOT and OVST
        1. 7.1.3.1 Mechanisms of HIPOT
        2. 7.1.3.2 Extended Validation of HIPOT
      4. 7.1.4 Hot Swap Response
      5. 7.1.5 High-frequency Response
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 PSpice® for TI
        2. 8.1.1.2 TINA-TI™ Simulation Software (Free Download)
        3. 8.1.1.3 TI Reference Designs
        4. 8.1.1.4 Analog Filter Designer
        5. 8.1.1.5 RES60A-Q1 Ratio and Voltage Error Calculator
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.4 Thermal Information

THERMAL METRIC(1) RES60A-Q1 UNIT
DWV (SOIC)
8 PINS
RθJA Junction-to-ambient thermal resistance 110.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 55.3 °C/W
RθJB Junction-to-board thermal resistance 53.0 °C/W
ψJT Junction-to-top characterization parameter 41.2 °C/W
ψJB Junction-to-board characterization parameter 51.6 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.