SLPS764B September   2024  – December 2025 RES60A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Absolute and Ratiometric Tolerances
      2. 6.3.2 Ultra-Low Noise
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Battery Stack Measurement
      2. 7.1.2 Gain Scaling the RES60A-Q1 With the RES11A-Q1
      3. 7.1.3 HIPOT and OVST
        1. 7.1.3.1 Mechanisms of HIPOT
        2. 7.1.3.2 Extended Validation of HIPOT
      4. 7.1.4 Hot Swap Response
      5. 7.1.5 High-frequency Response
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 PSpice® for TI
        2. 8.1.1.2 TINA-TI™ Simulation Software (Free Download)
        3. 8.1.1.3 TI Reference Designs
        4. 8.1.1.4 Analog Filter Designer
        5. 8.1.1.5 RES60A-Q1 Ratio and Voltage Error Calculator
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Maximum short-term overload voltage per divider, VD = VHVIN – VLVIN (100ms, TA = 25°C, DWV package)(2)(3) RES60A145 –2700 2700 V
RES60A210 –2700 2700
RES60A315 –2700 2700
RES60A410 –2700 2700
RES60A500 –2700 2700
RES60A610 –2700 2700
RES60A100 –2700 2700
Transient high-potential voltage, ac (50Hz, TA = 25°C, DWV package)(4)(5) RES60A145 –3000 3000 VRMS
RES60A210 –3000 3000
RES60A315 –3000 3000
RES60A410 –3000 3000
RES60A500 –3000 3000
RES60A610 –3000 3000
RES60A100 –3000 3000
Transient high-potential voltage, dc (TA = 25°C, DWV package)(4)(5) RES60A145 –4000 4000 VDC
RES60A210 –4000 4000
RES60A315 –4000 4000
RES60A410 –4000 4000
RES60A500 –4000 4000
RES60A610 –4000 4000
RES60A100 –4000 4000
TA Ambient temperature –55 150 °C
TJ Junction temperature –55 150 °C
Tstg Storage temperature –55 175 °C
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
Maximum short-term voltage permitted under transient conditions without performance degradation. Avoid sustained operation at or beyond these voltage levels, especially if the resulting self-heating causes TJ to exceed 150°C.
Tested in production, with ±2.7kV stress for 100ms, on each device.
Differential voltage from high-voltage domain (pins 1-4) to low-voltage domain (pins 5-8) of the package.
Total stress duration of 180s, accumulated over lifetime in increments of no longer than 60s periods, with duty cycle ≤ 20%. For example, after 60s of continuous stress, wait 240s for device temperature to settle before repeating the stress. Repeated transient high-potential voltage testing can lead to performance degradation or device damage.