SLUA749A July   2015  – May 2016 BQ76920 , BQ76930 , BQ76940

 

  1.   bq769x0 Family Top 10 Design Considerations
    1.     Trademarks
    2. 1  Host Controller Choice
    3. 2  Cell Count
    4. 3  Device Architecture
    5. 4  Cell Balance
    6. 5  XREADY
    7. 6  FET Drive
    8. 7  Load Detect
    9. 8  Low-Side Switching Considerations
    10. 9  REGSRC Supply
    11. 10 Random Cell Connection – Within Limits
    12. 11 References
  2.   Revision History

7 Load Detect

As described in the datasheet and shown in Figure 9, a load detect feature is built into the CHG pin and enabled when the CHG output is low. When using low side switching the CHG pin will be pulled up by a pack load through the gate drive network when the discharge FET is off. From the simplified circuit in Figure 10, it can be observed that the load must be a high impedance before the comparator will release. With common resistor values CHG may be approximately half the PACK- voltage less a couple diode drops. PACK- may need to be in the 3 to 5V range to remove the load detect condition. A load capacitance will take some time to discharge due to the large RCHG_OFF and series resistances. When a buffer is used for the charge FET drive, check its topology to see if the buffer circuit will provide a signal back to the CHG pin for load detect before relying on its operation.