SLUA749A July   2015  – May 2016 BQ76920 , BQ76930 , BQ76940

 

  1.   bq769x0 Family Top 10 Design Considerations
    1.     Trademarks
    2. Host Controller Choice
    3. Cell Count
    4. Device Architecture
    5. Cell Balance
    6. XREADY
    7. FET Drive
    8. Load Detect
    9. Low-Side Switching Considerations
    10. REGSRC Supply
    11. 10 Random Cell Connection – Within Limits
    12. 11 References
  2.   Revision History

XREADY

The bq76930 and bq76940 family members communicate balancing commands from the registers in the bottom group to the upper groups and voltages from the upper groups to the lower group register. The internal communication is monitored by an internal watchdog function. If too many of the communications have errors, the device sets the DEVICE_XREADY fault indicating it does not trust the voltages available from the upper groups. Since the voltages are not known, the device sets the DSG and CHG FET control signals off. The host can recognize the event, clear the fault and re-enable the FETs, but it cannot disable the watchdog feature. The minimum time that the FETs will be off may be approximately 100 ms. XREADY may be avoided by locating the power filter capacitors near the IC and careful board design, but operation of the feature cannot be prevented. XREADY is expected if the AFE is booted without cells connected to the upper groups. XREADY does not occur in the bq76920 since there is a single group.