SLUAA11B February   2020  – August 2021 BQ769142 , BQ76922 , BQ76942 , BQ76952

 

  1.   Trademarks
  2. 1Direct Commands
    1. 1.1 Alarm Enable - 0x66
    2. 1.2 Cell 1 Voltage - 0x14
    3. 1.3 Internal Temperature - 0x68
    4. 1.4 CC2 Current - 0x3A
  3. 2Subcommands
    1. 2.1 DEVICE_NUMBER - 0x0001
    2. 2.2 MANUFACTURING STATUS - 0x0057
    3. 2.3 FET_ENABLE - 0x0022
    4. 2.4 RESET - 0x0012
  4. 3Reading and Writing RAM Registers
    1. 3.1 Read 'Enabled Protections A'
    2. 3.2 Enter CONFIG_UPDATE Mode
    3. 3.3 Write 'Enabled Protections A'
    4. 3.4 Write 'VCell Mode'
    5. 3.5 Exit CONFIG_UPDATE Mode
  5. 4I2C With CRC
  6. 5SPI With CRC Examples
    1. 5.1 Direct Command Example: Alarm Enable - 0x66
    2. 5.2 Direct Command Example: Cell 1 Voltage - 0x14
    3. 5.3 Subcommand Example: Device Number - 0x0001
    4. 5.4 Subcommand Example: FET_ENABLE - 0x0022
    5. 5.5 Subcommand Example: RESET - 0x0012
    6. 5.6 RAM Register Read Example: Enabled Protections A
    7. 5.7 RAM Register Write Example: Enabled Protections A
  7. 6Simple Code Examples
  8. 7References
  9. 8Revision History

5 SPI With CRC Examples

The SPI interface on the BQ769x2 family can be enabled in the Settings:Configuration:Comm Type register. When changing to SPI mode, the default SPI output logic voltage level is 1.8V since it is referencing the internal voltage regulator of the device. To change the logic level, the REG1 LDO should be enabled and programmed to the desired voltage level and the SPI Configuration register should be programmed to 0x60 to enable the MISO_REG1 bit. Next, the SWAP_COMM_MODE() subcommand should be executed. If using BQStudio, then BQStudio should be restarted so that it can detect the new communication mode.

Some versions of the device will be available that are pre-configured to SPI mode.For information on the different part numbers available, see the device-specific data sheet.

The following examples cover some of the same commands covered in the I2C examples. Some important notes on the SPI interface protocol (with CRC):

  • SPI_CS is active low.
  • The first SPI packet is 8 bits. The first bit is the R/W bit followed by a 7-bit address.
  • The second packet is 8-bit data.
  • The third packet is the 8-bit CRC calculated over the first and second bytes.

All of the examples include multiple writes for each transaction. This method is used by the EV2400 and BQStudio to verify that the commands have been successfully written. This is because some transactions are ignored by the device if the internal oscillator is not running (if the device is in SLEEP mode) or if the processor is busy. Once the data on the MISO pin (which should reflect the data previously written on MOSI) shows the correct data, then it is confirmed the packets have been written successfully. A more detailed description of the SPI interface is available in the device-specific Technical Reference Manual.

There are a couple of differences to be aware of when using the BQ769x2 family in SPI mode versus I2C mode. While I2C mode supports block writes and reads, SPI mode supports only single byte transactions. While I2C mode supports clock stretching for direct commands, SPI mode does not have this feature so it is important to be aware of the direct command timing in addition to subcommand timing.