SLUAA81A October   2020  – February 2022 BQ769142 , BQ76922 , BQ76942 , BQ76952

 

  1.   Trademarks
  2. 1Introduction
  3. 2Cell Balancing Circuit Considerations
    1. 2.1 Internal Cell-Balancing Circuit Design
    2. 2.2 External Cell-Balancing Circuit Design Using N-Channel FETs
    3. 2.3 External Cell-Balancing Circuit Design Using P-Channel FETs
    4. 2.4 External Cell-Balancing Circuit Design Using BJTs
    5. 2.5 Voltage Measurement Accuracy During Balance
  4. 3Stand-Alone Balancing Algorithm and Settings
  5. 4Considerations for a Host-Balancing Algorithm
  6. 5Timing Information
  7. 6Debugging Common Issues With Cell Balancing
    1. 6.1 Using a Resistor Divider as a Cell Simulator
  8. 7References
  9. 8Revision History

Voltage Measurement Accuracy During Balance

Voltage measurements are generally very accurate while cell balancing is active, but there are some important factors to be aware of and to consider in the system design. Two things that should be considered are the time constant of the selected cell input filter components and the IR drop across the top cell input resistor that may impact the accuracy of the top cell measurement.

Time Constant of Filter Components: Voltage accuacy deviation during balancing should be minimal when the external cell input resistance and input capacitance are selected within the datasheet recommended values. Cell voltage is meausured during a 3ms interval and a small RC time constant will have very little impact. If larger component values are selected resulting in a large time constant, the voltage may not settle sufficiently during the mesaurement windows and a lower voltage will be measured.

IR Drop Across Top Cell Input Resistor: When cell balancing is active, there is additional current flow into the top cell input (VC16 for the BQ76952 for example), for each cell that is balancing. This additional current flow results in a small IR drop across the cell input resister of the top cell which results in a lower voltage reading during balancing. For example, if 8 cells are balancing simultaneously and 20 cell input resistors are used, this would result in a VC16 voltage measurement of 5mV lower than the actual cell voltage (35 uA * 20 Ω * 8 cells). The IR drop can be reduced by limiting the maximum number of cells allowed to balance simultaneously (Settings: Cell Balancing Config: Cell Balance Max Cells). The IR drop affects only the top cell measurement. If larger cell input resistors are used (like in the case using external balancing transistors where the maximum input resistor value of 100 Ω is advised), it may be good to use a smaller input resistor like 20 Ω on the VC16 pin to reduce the IR drop while using 100 Ω on the other pins.

Measurement Disturbance During COV/CUV Checks: Another potential cause of voltage measurement error during balancing is a disturbance to the voltage during periodic over-voltage and under-voltage checks. Every one second, cell balancing is disabled for ~20 ms to all COV and CUV checks to run on all cells. This disabling of the balancing is not synchronized to the cell measurement timing, so occasionally this can occur during the measurement of a nearby cell. This event generates a transient response that couples through the cell RC input network and can result in a measurement error of several mV lower than the actual voltage. This event occurs with low probability so it may typically only be observed once every several hundred seconds. One possible solution to work around this would be to filter a single measurement that differs from the measurement immediately before and after.