1 Introduction to the low-side/high-side protection solutions

Depending on where the protection FETs are located Figure 1-2, we can divide the battery packs into a low-side Figure 1-1 protection solution and a high-side protection solution.

Figure 1-1 illustrates a diagram of the low-side protection architecture, where both charge tube CFET and discharge tube DFET are positioned between B- and PACK- and situated at the low-side of the battery pack. AFE in TI’s BQ769x0 and BQ7690x families integrates a low-side driver.

Figure 1-2 illustrates a diagram of the high-side protection architecture, where both charge tube CFET and discharge tube DFET are positioned between B+ and PACK+ and situated at the high-side of the battery pack. AFE in TI’s BQ769x2 family integrates a high-side driver.

For the low-side protection solution, when CFET and DFET are turned off, the battery pack ground and system ground are no longer connected. Consequently, once protection is triggered and the charge/discharge FETs are turned off, direct communication between the battery side and the system side is no longer possible. To maintain communication, the isolated communication must be employed. This not only increases cost but also elevates power consumption, particularly during undervoltage protection. Excessive communication power consumption further exacerbates the situation for battery packs already operating under undervoltage conditions. Therefore, the low-side solution is primarily applied in cost-sensitive products without complex communication requirements.

In contrast to the low-side protection, the high-side protection solution maintains a common ground connection between the battery pack and system side even after protection is triggered. Therefore, communication between them can still be achieved without requiring additional isolation measures. Furthermore, the system becomes safer as the battery positive terminal is disconnected upon triggering the protection.