SLUSAS0F December   2011  – July 2025 BQ2946

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Sense Positive Input for V1
      2. 7.3.2 Output Drive, OUT
      3. 7.3.3 Supply Input, VDD
      4. 7.3.4 Thermal Pad, PWRPAD
    4. 7.4 Device Functional Modes
      1. 7.4.1 NORMAL Mode
      2. 7.4.2 OVERVOLTAGE Mode
      3. 7.4.3 Customer Test Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Application Configuration
      2. 8.1.2 29
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 System Example
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

10.1 Layout Guidelines

  1. Ensure the RC filters for the V1 and VDD pins are placed as close as possible to the target terminal, reducing the tracing loop area.
  2. The VSS pin should be routed to the CELL– terminal.
  3. Ensure the trace connecting the fuse to the gate, source of the NFET to the Pack is sufficient to withstand the current during a fuse blown event.