SLUSF18B October   2023  – May 2026 BQ25638

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Description (continued)
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power-On-Reset (POR)
      2. 7.3.2  Device Power Up from Battery
      3. 7.3.3  Device Power Up from Input Source
        1. 7.3.3.1 REGN LDO Power Up
        2. 7.3.3.2 Poor Source Qualification
        3. 7.3.3.3 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        4. 7.3.3.4 Converter Power-Up
        5. 7.3.3.5 Input Current Optimizer (ICO)
        6. 7.3.3.6 Switching Frequency and Dithering Feature
      4. 7.3.4  Power Path Management
        1. 7.3.4.1 Narrow VDC Architecture
        2. 7.3.4.2 Dynamic Power Management
          1. 7.3.4.2.1 Input Current Limit on ILIM Pin
        3. 7.3.4.3 High Impedance (HIZ) Mode
      5. 7.3.5  Battery Charging Management
        1. 7.3.5.1 Autonomous Charging Cycle
        2. 7.3.5.2 Battery Charging Profile
        3. 7.3.5.3 Charging Termination
        4. 7.3.5.4 Thermistor Qualification
          1. 7.3.5.4.1 Advanced Temperature Profile in Charge Mode
          2. 7.3.5.4.2 TS Pin Thermistor Configuration
          3. 7.3.5.4.3 Cold/Hot Temperature Window in OTG Mode
          4. 7.3.5.4.4 JEITA Charge Rate Scaling
          5. 7.3.5.4.5 TS_BIAS Pin
        5. 7.3.5.5 Charging Safety Timers
      6. 7.3.6  USB On-The-Go (OTG)
        1. 7.3.6.1 Boost OTG Mode
      7. 7.3.7  Integrated 12-bit ADC for Monitoring
      8. 7.3.8  Status Outputs (INT , PG , STAT)
        1. 7.3.8.1 PG Pin Power Good Indicator
        2. 7.3.8.2 Charging Status Indicator (STAT)
        3. 7.3.8.3 Interrupt to Host (INT)
      9. 7.3.9  BATFET Control
        1. 7.3.9.1 Shutdown Mode
        2. 7.3.9.2 Ultra-Low Power Mode (ULPM)
        3. 7.3.9.3 System Power Reset
      10. 7.3.10 Protections
        1. 7.3.10.1 Voltage and Current Monitoring in Battery Only and HIZ Modes
          1. 7.3.10.1.1 Battery Overcurrent Protection
          2. 7.3.10.1.2 Battery Undervoltage Lockout
        2. 7.3.10.2 Voltage and Current Monitoring in Buck Mode
          1. 7.3.10.2.1 Input Overvoltage
          2. 7.3.10.2.2 System Overvoltage Protection (SYSOVP)
          3. 7.3.10.2.3 Forward Converter Cycle-by-Cycle Current Limit
          4. 7.3.10.2.4 System Short
          5. 7.3.10.2.5 Battery Overvoltage Protection (BATOVP)
          6. 7.3.10.2.6 Sleep and Poor Source Comparators
        3. 7.3.10.3 Voltage and Current Monitoring in Boost Mode
          1. 7.3.10.3.1 Boost Mode Overvoltage Protection
          2. 7.3.10.3.2 Boost Mode Duty Cycle Protection
          3. 7.3.10.3.3 Boost Mode PMID Undervoltage Protection
          4. 7.3.10.3.4 Boost Mode Battery Undervoltage
          5. 7.3.10.3.5 Boost Converter Cycle-by-Cycle Current Limit
          6. 7.3.10.3.6 Boost Mode SYS Short
        4. 7.3.10.4 Thermal Regulation and Thermal Shutdown
          1. 7.3.10.4.1 Thermal Protection in Buck Mode
          2. 7.3.10.4.2 Thermal Protection in Boost Mode
          3. 7.3.10.4.3 Thermal Protection in Battery-only Mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Host Mode and Default Mode
      2. 7.4.2 Register Bit Reset
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
        1. 7.5.1.1 Data Validity
        2. 7.5.1.2 START and STOP Conditions
        3. 7.5.1.3 Byte Format
        4. 7.5.1.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 7.5.1.5 Target Address and Data Direction Bit
        6. 7.5.1.6 Single Write and Read
        7. 7.5.1.7 Multi-Write and Multi-Read
  9. 8 Register Maps
    1. 8.1 BQ25638 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Input Capacitor
        3. 9.2.2.3 Output Capacitor
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1.     PACKAGE OPTION ADDENDUM
    2. 12.1 Tape and Reel Information
    3. 12.2 Mechanical Data
7.3.10.2.6 Sleep and Poor Source Comparators

The sleep comparator is used to suspend the converter if the adapter voltage is insufficient to maintain buck converter operation while charging the battery. If VVBUS falls below VBAT + VSLEEP the converter stops switching, the PG pin transitions high. If VVBUS rises back above VBAT + VSLEEPZ, the converter restarts, the PG pin transitions low.

If VVBUS falls below VPOORSRC, the converter stops switching and the PG pin transitions high (if not already suspended and high due to the sleep comparator), and the VBUS_STAT transitions to 000 and the device transitions to battery-only mode. If VVBUS rises above VPOORSRC, it indicates a new adapter attach, and poor source qualification is run. VBUS_STAT and the PG pin state will be is determined by the adapter attach sequence as outlined in Section 7.3.3.