SLUSFL5 March   2025 UCC5350L-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Function
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings (Automotive)
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics
    10. 5.10 Switching Characteristics
    11. 5.11 Insulation Characteristics Curves
    12. 5.12 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Propagation Delay, Inverting, and Noninverting Configuration
      1. 6.1.1 CMTI Testing
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Supply
      2. 7.3.2 Input Stage
      3. 7.3.3 Output Stage
      4. 7.3.4 Protection Features
        1. 7.3.4.1 Undervoltage Lockout (UVLO)
        2. 7.3.4.2 Active Pulldown
        3. 7.3.4.3 Short-Circuit Clamping
        4. 7.3.4.4 Active Miller Clamp
    4. 7.4 Device Functional Modes
      1. 7.4.1 ESD Structure
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Designing IN+ and IN– Input Filter
        2. 8.2.2.2 Gate-Driver Output Resistor
        3. 8.2.2.3 Estimate Gate-Driver Power Loss
        4. 8.2.2.4 Estimating Junction Temperature
        5. 8.2.2.5 Selecting VCC1 and VCC2 Capacitors
          1. 8.2.2.5.1 Selecting a VCC1 Capacitor
          2. 8.2.2.5.2 Selecting a VCC2 Capacitor
          3. 8.2.2.5.3 Application Circuits with Output Stage Negative Bias
      3. 8.2.3 Application Curve
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 PCB Material
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Certifications
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

3 Description

The UCC5350L-Q1 is a single-channel, isolated gate driver with 10A source and 10A sink typical peak current designed to drive MOSFETs, IGBTs, and SiC MOSFETs. The UCC5350L-Q1 has the option for Miller clamp. The CLAMP pin is used to connect the transistor gate to an internal FET besides the output to prevent false turn-on caused by Miller current. The UCC5350L-Q1 is available in a 14mm wide body SOIC-8 (DWL) package and can support isolation voltage up to 5kVRMS. The input side is isolated from the output side with SiO2 capacitive isolation technology with longer than 40 years isolation barrier lifetime. The UCC5350L-Q1 is a good fit for driving IGBTs or MOSFETs in applications such as high-voltage traction inverters and on-board chargers. Compared to an optocoupler, the device has lower part-to-part skew, lower propagation delay, higher operating temperature, and higher CMTI.

Device Information
PART VERSION FEATURES PACKAGE(1) BODY SIZE (NOM)

UCC5350MCQDWL-Q1

 Miller Clamp, 12V UVLO DWL (SOIC-8) 14mm × 6.4mm
(1) For all available packages, see Section 13.
UCC5350L-Q1 Functional Block Diagram Functional Block Diagram