SLUSFL5 March   2025 UCC5350L-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Function
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings (Automotive)
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics
    10. 5.10 Switching Characteristics
    11. 5.11 Insulation Characteristics Curves
    12. 5.12 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Propagation Delay, Inverting, and Noninverting Configuration
      1. 6.1.1 CMTI Testing
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Supply
      2. 7.3.2 Input Stage
      3. 7.3.3 Output Stage
      4. 7.3.4 Protection Features
        1. 7.3.4.1 Undervoltage Lockout (UVLO)
        2. 7.3.4.2 Active Pulldown
        3. 7.3.4.3 Short-Circuit Clamping
        4. 7.3.4.4 Active Miller Clamp
    4. 7.4 Device Functional Modes
      1. 7.4.1 ESD Structure
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Designing IN+ and IN– Input Filter
        2. 8.2.2.2 Gate-Driver Output Resistor
        3. 8.2.2.3 Estimate Gate-Driver Power Loss
        4. 8.2.2.4 Estimating Junction Temperature
        5. 8.2.2.5 Selecting VCC1 and VCC2 Capacitors
          1. 8.2.2.5.1 Selecting a VCC1 Capacitor
          2. 8.2.2.5.2 Selecting a VCC2 Capacitor
          3. 8.2.2.5.3 Application Circuits with Output Stage Negative Bias
      3. 8.2.3 Application Curve
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 PCB Material
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Certifications
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

7.3.3 Output Stage

The output stage of the UCC5350L-Q1 features a pull-up structure that delivers the highest peak-source current when it is most needed which is during the Miller plateau region of the power-switch turn-on transition (when the power-switch drain or collector voltage experiences dV/dt). The output stage pull-up structure features a P-channel MOSFET and an additional pull-up N-channel MOSFET in parallel. The function of the N-channel MOSFET is to provide a brief boost in the peak-sourcing current, which enables fast turn-on. Fast turn-on is accomplished by briefly turning on the N-channel MOSFET during a narrow instant when the output is changing states from low to high. Table 7-1 lists the typical internal resistance values of the pull-up and pull-down structure.

Table 7-1 UCC5350L-Q1 On-Resistance
DEVICE OPTION RNMOS ROH ROL RCLAMP UNIT
UCC5350L-Q1 1.54 12 0.26 0.26 Ω

The ROH parameter is a DC measurement and is representative of the on-resistance of the P-channel device only. This parameter is only for the P-channel device, because the pull-up N-channel device is held in the OFF state in DC condition and is turned on only for a brief instant when the output is changing states from low to high. Therefore, the effective resistance of the UCC5350L-Q1 pull-up stage during this brief turn-on phase is much lower than what is represented by the ROH parameter, which yields a faster turn-on. The turn-on-phase output resistance is the parallel combination ROH || RNMOS.

The pull-down structure in the UCC5350L-Q1 is simply composed of an N-channel MOSFET. For Miller Clamp, an additional FET is connected in parallel with the pull-down structure when the CLAMP and OUT pins are connected to the gate of the IGBT or MOSFET.The output is capable of delivering, or sinking, 5-A peak current pulses. The output voltage swing between VCC2 and VEE2 provides rail-to-rail operation.

UCC5350L-Q1 Output StageFigure 7-4 Output Stage