SLUSFL5 March   2025 UCC5350L-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Function
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings (Automotive)
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics
    10. 5.10 Switching Characteristics
    11. 5.11 Insulation Characteristics Curves
    12. 5.12 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Propagation Delay, Inverting, and Noninverting Configuration
      1. 6.1.1 CMTI Testing
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Supply
      2. 7.3.2 Input Stage
      3. 7.3.3 Output Stage
      4. 7.3.4 Protection Features
        1. 7.3.4.1 Undervoltage Lockout (UVLO)
        2. 7.3.4.2 Active Pulldown
        3. 7.3.4.3 Short-Circuit Clamping
        4. 7.3.4.4 Active Miller Clamp
    4. 7.4 Device Functional Modes
      1. 7.4.1 ESD Structure
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Designing IN+ and IN– Input Filter
        2. 8.2.2.2 Gate-Driver Output Resistor
        3. 8.2.2.3 Estimate Gate-Driver Power Loss
        4. 8.2.2.4 Estimating Junction Temperature
        5. 8.2.2.5 Selecting VCC1 and VCC2 Capacitors
          1. 8.2.2.5.1 Selecting a VCC1 Capacitor
          2. 8.2.2.5.2 Selecting a VCC2 Capacitor
          3. 8.2.2.5.3 Application Circuits with Output Stage Negative Bias
      3. 8.2.3 Application Curve
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 PCB Material
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Certifications
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

5.6 Insulation Specifications

PARAMETER TEST CONDITIONS SPECIFICATION UNIT
GENERAL
CLR External clearance(1) Shortest terminal-to-terminal distance through air > 14.7 mm
CPG External Creepage(1) Shortest terminal-to-terminal distance across the package surface > 15.7 mm
DTI Distance through the insulation Minimum internal gap (internal clearance) > 21 µm
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 > 600 V
Material Group According to IEC 60664–1 I
Overvoltage Category per IEC 60664–1 Rated mains voltage ≤ 600 VRMS I-IV
Overvoltage Category per IEC 60664–1 Rated mains voltage ≤ 1000 VRMS I-III
DIN EN IEC 60747-17 (VDE 0884-17)
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 2121 VPK
VIOWM Maximum isolation working voltage AC voltage (sine wave); time-dependent dielectric breakdown (TDDB) test; see Figure 1 1500 VRMS
DC voltage 2121 VDC
VIOTM Maximum transient isolation voltage VTEST = VIOTM, t = 60 s (qualification test)
VTEST= 1.2 × VIOTM, t = 1 s (100% production test)		 7000 VPK
VIOSM Maximum surge isolation voltage(2) Test method per IEC 60065, 1.2/50 µs waveform, VTEST = 1.6 × VIOSM (qualification) 8000 VPK
qpd Apparent charge(3) Method a: After I/O safety test subgroup 2/3, Vini =VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM, tm = 10 s ≤ 5 pC
Method a: After environmental tests subgroup 1,Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM, tm = 10 s ≤ 5
Method b1: At routine test (100% production) and preconditioning (type test), Vini = VIOTM, tini = 1 s; Vpd(m) = 1.875 × VIORM = x VPK, tm = 1 s ≤ 5
CIO Barrier capacitance, input to output(4) VIO = 0.5 × sin (2πft), f = 1 MHz ~1.5 pF
RIO Insulation resistance, input to output(4) VIO = 500 V,  TA = 25°C ≥ 1012 Ω
VIO = 500 V,  100°C ≤ TA ≤ 125°C ≥ 1011
VIO = 500 V at  TS = 150°C ≥ 109
Pollution degree 2
Climatic category 40/125/21
UL 1577
VISO Withstand isolation voltage VTEST = VISO = 5000 VRMS, t = 60 s (qualification), VTEST = 1.2 × VISO = 6000 VRMS, t = 1 s (100% production) 5000 VRMS
(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as inserting grooves and ribs on the PCB are used to help increase these specifications.
(2) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(3) Apparent charge is electrical discharge caused by a partial discharge (pd).
(4) All pins on each side of the barrier tied together creating a two-pin device.